Image sensor having stress releasing structure and method of forming same
A semiconductor structure includes a sensor chip. The sensor chip includes a pixel array region, a bonding pad region, and a periphery region surrounding the pixel array region. The semiconductor structure further includes a stress-releasing trench, wherein the stress-releasing trench is in the periphery region, and the stress-releasing trench fully surrounds a perimeter of the pixel array region and the bonding pad region.
1. A semiconductor structure comprising:
a sensor chip comprising:
a pixel array region,
a bonding pad region, and
a periphery region surrounding the pixel array region; and
a stress-releasing trench, wherein the stress-releasing trench is in the periphery region, the stress-releasing trench fully surrounds a perimeter of the pixel array region and the bonding pad region, and a space between a first side of the pixel array region and the periphery region is free of the bonding pad region.
2. The semiconductor structure of claim 1 , further comprising a second stress-releasing trench surrounding the stress-releasing trench.
3. The semiconductor structure of claim 1 , wherein the stress-releasing trench is a continuous trench.
4. The semiconductor structure of claim 1 , wherein the stress-releasing trench is discontinuous.
5. The semiconductor structure of claim 1 , wherein the bonding pad region is between the stress-releasing trench and a second side of the pixel array region.
6. The semiconductor structure of claim 1 , wherein a top-most surface of a bonding pad in the bonding pad region is below a top-most surface of the stress-releasing trench.
7. The semiconductor structure of claim 1 , further comprising a plurality of bonding pads in the bonding pad region.
8. A semiconductor structure comprising:
a sensor chip comprising:
a pixel array region, wherein the pixel array region comprises a plurality of photosensitive elements,
a bonding pad region, and
a periphery region surrounding the pixel array region; and
a plurality of stress-releasing trenches, wherein each of the plurality of stress-releasing trenches is in the periphery region and surrounds a perimeter of the pixel array region and the bonding pad region, and a bottom-most surface of a photosensitive element of the plurality of photosensitive elements is below a bottom-most surface of a stress-releasing trench of the plurality of stress-releasing trenches.
9. The semiconductor structure of claim 8 , wherein each of the plurality of stress-releasing trenches is discontinuous.
10. The semiconductor structure of claim 8 , wherein a distance between adjacent stress-releasing trenches of the plurality of stress-releasing trenches is less than about 100 microns (μm).
11. The semiconductor structure of claim 8 , wherein the plurality of stress-releasing trenches comprises a first stress-releasing trench and a second stress-releasing trench, wherein segments of the first stress-releasing trench overlap with segments of the second stress-releasing trench in a direction parallel to a top surface of the sensor chip.
12. The semiconductor structure of claim 8 , wherein the plurality of stress-releasing trenches comprises a first stress-releasing trench and a second stress-releasing trench, wherein gaps between segments of the first stress-releasing trench are offset with respect to gaps between segments of the second stress-releasing trench in a direction parallel to a top surface of the sensor chip.
13. The semiconductor structure of claim 8 , wherein at least one of the plurality of stress-releasing trenches has tapered sidewalls.
14. The semiconductor structure of claim 8 , wherein at least one of the plurality of stress-releasing trenches has sidewalls perpendicular to a top surface of the senor chip.
15. A semiconductor structure comprising:
a sensor wafer comprising:
a first semiconductor substrate;
a plurality of photosensitive elements in a pixel array region of the first semiconductor substrate;
a plurality of isolation structures, wherein each of the plurality of isolation structures is between adjacent photosensitive elements of the plurality of photosensitive elements;
a first interconnect structure on the front side of the first semiconductor substrate; and
a stress-releasing trench structure in the first semiconductor substrate surrounding the pixel array region, wherein the stress-releasing trench structure is within a trench that extends through the first semiconductor substrate, and a height of the stress-releasing trench is greater than a height of an isolation structure of the plurality of isolation structures.
16. The semiconductor structure of claim 15 , further comprising a device wafer bonded to the sensor wafer, wherein the device wafer comprises an active device.
17. The semiconductor structure of claim 16 , wherein the sensor wafer further includes an interconnect structure, and the interconnect structure is between the stress-releasing trench and the device wafer.
18. The semiconductor structure of claim 15 , wherein the plurality of photosensitive elements is in a front side of the semiconductor substrate, and the stress-releasing trench structure extends from a back side of the first semiconductor substrate, and the back side of the first semiconductor substrate is opposite the front side of the first semiconductor substrate.
19. The semiconductor structure of claim 15 , wherein the sensor wafer further comprises a bonding pad region spaced from the plurality of photosensitive elements.
20. The semiconductor structure of claim 19 , wherein the stress-releasing trench surrounds the bonding pad region.