Etch profile control of gate contact opening

1. A method comprising:

forming a gate structure over a semiconductor substrate;

etching back the gate structure;

forming a gate dielectric cap over the etched back gate structure;

depositing an etch-resistant layer over the gate dielectric cap;

depositing a contact etch stop layer over the gate dielectric cap and an interlayer dielectric (ILD) layer over the contact etch stop layer;

performing a first etching process to form a gate contact opening extending through the ILD layer and terminating prior to reaching the etch-resistant layer;

performing a second etching process to deepen the gate contact opening, wherein the second etching process etches the etch-resistant layer at a slower etch rate than etching the contact etch stop layer; and

forming a gate contact in the deepened gate contact opening.

2. The method of claim 1 , wherein the second etching process etches the gate dielectric cap at a faster etch rate than etching the etch-resistant layer.

3. The method of claim 1 , wherein the gate dielectric cap is formed of a same material as the contact etch stop layer.

4. The method of claim 1 , wherein the gate dielectric cap and the contact etch stop layer are nitride-based.

5. The method of claim 1 , wherein the etch-resistant layer is oxide-based.

6. The method of claim 1 , wherein the etch-resistant layer has a thickness less than a thickness of the contact etch stop layer.

7. The method of claim 1 , wherein the etch-resistant layer has a thickness less than a maximal thickness of the gate dielectric cap.

8. The method of claim 1 , wherein the etch-resistant layer has a thickness in a range from about 1 Angstroms to about 50 Angstroms.

9. The method of claim 1 , wherein the etch-resistant layer is deposited using atomic layer deposition (ALD) or plasma enhanced chemical vapor deposition (PECVD).

10. The method of claim 1 , wherein the first etching process is a plasma etching process using a plasma generated from a hydrogen-free gaseous mixture.

11. The method of claim 1 , wherein the second etching process is a plasma etching process using a plasma generated from a hydrogen-containing gaseous mixture.

12. The method of claim 11 , wherein the hydrogen-containing gaseous mixture is a mixture of a fluorine-containing gas and a hydrogen gas.

13. The method of claim 12 , wherein the fluorine-containing gas is a CHF 3 gas, a CF 4 gas, a C x H y F z gas, or a combination thereof, wherein x, y and z are greater than zero.

14. A method comprising:

forming a first gate dielectric cap over a first gate structure and a second gate dielectric cap over a second gate structure;

depositing an etch-resistant layer over the first gate dielectric cap and the second gate dielectric cap;

depositing a contact etch stop layer over the etch-resistant layer, and an interlayer dielectric (ILD) layer over the contact etch stop layer;

performing a first etching process to form a first gate contact opening and a second gate contact opening extending through the ILD layer, wherein the first gate contact opening has a smaller width than the second gate contact opening;

performing a second etching process to extend the first and second gate contact openings toward the first and second gate structures, wherein the second etching process etches the etch-resistant layer at a slower etch rate than etching the contact etch stop layer, wherein after the second etching process etches through the etch-resistant layer, a sidewall profile of the first gate contact opening becomes more vertical than before etching the etch-resistant layer; and

after performing the second etching process, forming a first gate contact in the first gate contact opening and a second gate contact in the second gate contact opening.

15. The method of claim 14 , wherein the first etching process results in the first gate contact opening having a smaller depth than the second gate contact opening.

16. The method of claim 14 , wherein after the second etching process etches through the etch-resistant layer, a depth difference between the first and second gate contact openings becomes less than before performing the second etching process.

17. The method of claim 14 , wherein the second etching process uses a gas mixture with a hydrogen gas, and the first etching process is free of the hydrogen gas.

18. A method comprising:

forming source/drain regions on a substrate;

forming a gate structure laterally between the source/drain regions, and gate spacers on either side of the gate structure;

forming a gate dielectric cap on the gate structure and the gate spacers;

forming source/drain contacts on the source/drain regions, with the gate dielectric cap interposing the source/drain contacts;

forming an oxide-based etch-resistant layer over the gate dielectric cap;

forming a nitride-based etch stop layer over the oxide-based etch-resistant layer;

forming an interlayer dielectric (ILD) layer over the nitride-based etch stop layer;

performing a first etching process to form a gate contact opening in the ILD layer;

performing a second etching process to deepen the gate contact opening, wherein the second etching process etches the oxide-based etch-resistant layer at a slower etch rate than etching the nitride-based etch stop layer; and

forming a gate contact in the deepened gate contact opening, the gate contact extending through the ILD layer, the nitride-based etch stop layer, the oxide-based etch-resistant layer, and the gate dielectric cap to the gate structure.

19. The method of claim 18 , wherein the oxide-based etch-resistant layer is thinner than the nitride-based etch stop layer.

20. The method of claim 18 , wherein the gate structure has a top surface lower than top surfaces of the gate spacers.