Dual-layer channel transistor and methods of forming same

1. A transistor, comprising:

a substrate;

a word line disposed on the substrate;

a gate dielectric layer disposed on the word line;

a dual-layer semiconductor channel comprising:

a first channel layer disposed on the gate dielectric layer and having a first electrical resistance; and

a second channel layer having a second electrical resistance and that is disposed on the first channel layer such that the second channel layer contacts side and top surfaces of the first channel layer; and

a source electrode and a drain electrode that are electrically coupled to the second channel layer,

wherein the first electrical resistance is higher than the second electrical resistance.

2. The transistor of claim 1 , wherein:

the first channel layer comprises amorphous-Si, Ga 2 O 3 , GZO, or a first type of IGZO;

the second channel layer comprises poly-Si, InO, ITO, SnO 2 , or a first type of IGZO; and

the second type of IGZO has a higher Ga at % or a lower In at % than the first type of IGZO.

3. The transistor of claim 1 , wherein the source electrode and drain electrode overlap opposing portions of the first channel layer in a vertical direction.

4. The transistor of claim 1 , wherein the first channel layer has a higher band gap than the second channel layer.

5. The transistor of claim 1 , wherein the first channel layer has a different threshold voltage from the second channel layer.

6. The transistor of claim 1 , wherein the first channel layer has a higher Ga at % or a lower In at % than the second channel layer.

7. The transistor of claim 1 , further comprising a first dielectric layer disposed on the substrate, wherein the word line is embedded in the first dielectric layer.

8. The transistor of claim 7 further comprising a second dielectric layer disposed on the second channel layer and embedding the source electrode and the drain electrode.

9. The transistor of claim 1 , wherein a width of the first channel layer is less than a width of the word line.

10. The transistor of claim 9 , wherein the source electrode and drain electrode overlap opposing portions of the word line, in a vertical direction perpendicular to a plane of the substrate.

11. The transistor of claim 9 , wherein a width between the source electrode and drain electrode is greater than a width of the word line.

12. A transistor, comprising:

a substrate;

a word line disposed on the substrate;

a gate dielectric layer disposed on the word line;

a dual-layer channel disposed on the gate dielectric layer and comprising:

a first channel layer disposed on the gate dielectric layer; and

a second channel layer comprising a semiconductor material and disposed on the first channel layer, such that the second channel layer contacts side and top surfaces of the first channel layer; and

a source electrode and a drain electrode that are electrically coupled to the second channel layer,

wherein in response to a voltage being applied to the word line, the first channel layer has a first electrical resistance and the second channel layer has a second electrical resistance that is higher than the first electrical resistance,

wherein the first channel layer comprises a metal or metal alloy having the first electrical resistance.

13. The transistor of claim 12 , wherein the first channel layer is configured to reduce a total resistance of an effective channel of the transistor by shortening the length of a conductive path through the dual-layer channel.

14. The transistor of claim 12 , wherein a width of the first channel layer is less than a width of the word line.

15. The transistor of claim 14 , wherein the source electrode and drain electrode overlap opposing portions of the word line, in a vertical direction perpendicular to a plane of the substrate.

16. The transistor of claim 12 , wherein the source electrode and drain electrode overlap opposing portions of the first channel layer in a vertical direction.

17. The transistor of claim 16 , wherein a width between the source electrode and drain electrode is greater than a width of the word line.

18. The transistor of claim 12 , further comprising a first dielectric layer disposed on the substrate, wherein the word line is embedded in the first dielectric layer.

19. The transistor of claim 18 , further comprising a second dielectric layer disposed on the second channel layer and embedding the source electrode and the drain electrode.

20. A method of forming a semiconductor device comprising:

depositing a first dielectric layer on a semiconductor substrate;

forming a word line in the first dielectric layer;

depositing a gate dielectric layer over the word line;

forming a dual-layer channel on the gate dielectric layer, by:

depositing amorphous-Si, Ga 2 O 3 , GZO, or a second type of IGZO on the gate dielectric layer to form a first channel layer having a first electrical resistance; and

depositing poly-Si, InO, ITO, SnO 2 , or a first type of IGZO on the first channel layer to form a second channel layer having a second electrical resistance that is different from the first electrical resistance, such that the second channel layer contacts side and top surfaces of the first channel layer, wherein the second channel layer comprises a semiconductor material,

depositing second dielectric layer on the second channel layer; and

forming a source electrode and a drain electrode in the second dielectric layer,

wherein the first type of IGZO has a lower Ga at % or a higher In at % than the second type of IGZO.