IP Library Granted Patent US 12,456,651
Granted Patent B2
US 12,456,651 · App. 17/231,074 · Granted Oct 28, 2025

Semiconductor die forming and packaging method using ultrashort pulse laser micromachining

Inventors: Jin Won Jeong (Seoul, KR); Jae Sik Choi (Cheongju-si, KR); Byeung Soo Song (Sejong-si, KR)
Assignee: MagnaChip Semiconductor, Ltd.
H01L21/78H01L21/268H01L21/3043H01L21/67092
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Quick Facts
Patent No.
US 12,456,651
App. No.
17/231,074
Granted
Oct 28, 2025
Kind
B2
Abstract

A semiconductor die forming method includes preparing a wafer, forming a low-k dielectric layer on the wafer, forming a metal pad on the low-k dielectric layer, forming a passivation layer on the metal pad, patterning the passivation layer, laser grooving the low-k dielectric layer using an ultrashort pulse laser, and cutting the wafer by mechanical sawing to form one or more semiconductor dies.

Claims (53)

1. A method for forming a semiconductor die, the method comprising:

providing a substrate;

forming a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer being a low-k dielectric layer;

forming a metal wire on the first interlayer dielectric layer;

forming a second interlayer dielectric layer on the metal wire;

forming a metal pad on the second interlayer dielectric layer;

forming a passivation dielectric layer on the metal pad;

patterning the passivation dielectric layer to expose the metal pad;

forming a metal bump on the exposed metal pad;

removing the patterned passivation dielectric layer adjacent to a scribe line region;

laser grooving the second interlayer dielectric layer and the low-k dielectric layer exposed by removing the patterned passivation dielectric layer from the scribe line region using an ultrashort pulse laser; and

cutting the substrate by mechanical sawing to form one or more semiconductor dies,

wherein the second interlayer dielectric layer is exposed by removing the patterned passivation dielectric layer adjacent to the scribe line region, and

wherein a light source of the ultrashort pulse laser directly irradiates the second interlayer dielectric layer to remove the second interlayer dielectric layer.

2. The method of claim 1 , wherein a pulse width of the ultrashort pulse laser is in picoseconds or femtoseconds, and

wherein the ultrashort pulse laser operates at ultraviolet or infrared wavelengths.

3. The method of claim 1 , wherein the laser grooving of the second interlayer dielectric layer and the low-k dielectric layer includes;

performing a first low-power laser grooving to form a first groove region on an edge of the scribe line region; and

performing a second low-power laser grooving to form a second groove region on the scribe line region, and

wherein a U-shape zone is formed by the laser grooving of the low-k dielectric layer.

4. The method of claim 3 , wherein a slope of a side surface of the first groove region and a slope of a side surface of the second groove region are different from each other.

5. The method of claim 3 , wherein a thickness of the second groove region is greater than a thickness of the first groove region.

6. The method of claim 1 further comprising:

attaching the one or more semiconductor dies to a display flexible substrate using an anisotropic conductive film including a conductive ball.

7. The method of claim 1 , wherein the laser grooving of the low-k dielectric layer is performed until the one or more semiconductor dies are exposed.

8. The method of claim 1 , wherein the removing of the patterned passivation dielectric layer adjacent to the scribe line region is performed by a dry etching process.

9. A method for forming a semiconductor die, the method comprising:

providing a substrate;

forming a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer being a low-k dielectric layer;

forming a metal wire on the first interlayer dielectric layer;

forming a second interlayer dielectric layer on the metal wire;

forming a metal pad on the second interlayer dielectric layer;

forming a passivation dielectric layer on the metal pad;

patterning the passivation dielectric layer to expose the metal pad;

removing the patterned passivation dielectric layer adjacent to a scribe line region;

laser grooving the second interlayer dielectric layer and the low-k dielectric layer not covered by the patterned passivation dielectric layer using an ultrashort pulse laser; and

cutting the substrate by mechanical sawing to form one or more semiconductor dies,

wherein the laser grooving of the second interlayer dielectric layer and the first interlayer dielectric layer comprises:

performing a first low-power laser grooving to form a first groove region at an edge of the scribe line region, the first groove region being formed in the first and second interlayer dielectric layers; and

performing a second low-power laser grooving to form a second groove region on the scribe line region,

wherein a slope of a side surface of the low-k dielectric layer and a slope of a side surface of the semiconductor die are different from each other.

10. The method of claim 9 , further comprising:

disposing one of the one or more semiconductor dies on a display flexible substrate.

11. The method of claim 10 , wherein the disposing of one of the one or more semiconductor dies comprises:

attaching the one or more semiconductor dies to the display flexible substrate using an anisotropic conductive film (ACF) including conductive balls.

12. The method of claim 9 , wherein a slope of a side surface of the low-k dielectric layer has two different slopes.

13. The method of claim 9 , wherein a groove region having an inverted trapezoidal shape is formed by the laser grooving of the low-k dielectric layer.

14. The method of claim 9 , wherein a chip packaging method is used to package a Chip-on-Plastic or Chip-on-Panel packaging.

15. The method of claim 9 , further comprising:

forming a metal bump on the exposed metal pad,

wherein the second interlayer dielectric layer is exposed by removing the patterned passivation dielectric layer adjacent to the scribe line region, and

wherein the laser grooving of the second interlayer dielectric layer comprises directly irradiating the exposed second interlayer dielectric layer with a light source of the ultrashort pulse laser to remove the second interlayer dielectric layer.

16. The method of claim 9 , wherein the passivation dielectric layer further comprises a silicon oxide film.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2025
From: MAGNACHIP MIXED-SIGNAL, LTD.
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 071813/0800 →
NUNC PRO TUNC ASSIGNMENT Recorded Mar 14, 2024
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: MAGNACHIP MIXED-SIGNAL, LTD.
Reel/Frame 066878/0875 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2021
From: JEONG, JIN WON; CHOI, JAE SIK; SONG, BYEUNG SOO
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 055926/0242 →
Priority Claims (1)
KR 10-2020-0078137 · Jun 26, 2020 · national
Continuity (1)
Related Publication 20210407854A1 · Dec 30, 2021
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