IP Library › Granted Patent US 12,222,881
Granted Patent B2
US 12,222,881 · App. 17/231,152 · Granted Feb 11, 2025

Logical physical layer interface specification support for PCie 6.0, cxl 3.0, and UPI 3.0 protocols

Inventors: Swadesh Choudhary (Mountain View, CA); Mahesh Wagh (Portland, OR); Debendra Das Sharma (Saratoga, CA)
Assignee: INTEL CORPORATION
G06F13/382G06F11/1048G06F13/4018G06F13/4059G06F13/4068
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Quick Facts
Patent No.
US 12,222,881
App. No.
17/231,152
Granted
Feb 11, 2025
Kind
B2
Abstract

In one embodiment, an apparatus includes: a first link layer circuit to perform link layer functionality for a first communication protocol; and a logical physical (logPHY) circuit coupled to the first link layer circuit via a logical PHY interface (LPIF) link, the logPHY circuit to communicate with the first link layer circuit in a flit mode in which the first information is communicated in a fixed width size and to communicate with another link layer circuit in a non-flit mode. Other embodiments are described and claimed.

Claims (35)

1. An apparatus comprising:

a first link layer circuit to perform link layer functionality for a first communication protocol;

a second link layer circuit to perform link layer functionality for a second communication protocol;

a selection circuit coupled to the first link layer circuit via a first logical PHY interface (LPIF) link and coupled to the second link layer circuit via a second LPIF link, to provide first information from the first link layer circuit to a logical physical (logPHY) circuit and second information from the second link layer circuit to the logPHY circuit; and

the logPHY circuit coupled to the selection circuit via a third LPIF link, wherein the logPHY circuit is to communicate with the first link layer circuit in a flit mode in which the first information is communicated in a fixed width size and communicate with the second link layer circuit in a non-flit mode in which the second information is communicated in a variable width size,

wherein the first link layer circuit is to start a flit header in a middle of a flit and send the flit with the flit header to the logPHY circuit.

2. The apparatus of claim 1 , wherein the logPHY circuit is to communicate a flit mode signal to the first link layer circuit to cause the first link layer circuit to communicate the first information in the flit mode.

3. The apparatus of claim 1 , further comprising a media access control (MAC) circuit comprising the logPHY circuit to communicate with the first link layer circuit in the flit mode and to communicate with the second link layer circuit in the non-flit mode.

4. The apparatus of claim 1 , wherein the logPHY circuit is to receive a first indication from the first link layer circuit that a first flit is a no operation (NOP) flit, wherein in response to the first indication, the logPHY circuit is to not store the NOP flit in a replay buffer.

5. The apparatus of claim 1 , wherein the logPHY circuit comprises an error detection circuit, and wherein in response to detection of an error in an incoming flit, the logPHY circuit is to send a cancellation message to the first link layer circuit to cause the first link layer circuit to drop the incoming flit.

6. The apparatus of claim 5 , wherein the logPHY circuit is to send the cancellation message within a predetermined number of clock cycles after the logPHY circuit sent the incoming flit to the first link layer circuit.

7. The apparatus of claim 5 , wherein the logPHY circuit further comprises an error correction circuit to correct the error in the incoming flit, the logPHY circuit to send the corrected incoming flit to the first link layer circuit.

8. The apparatus of claim 1 , wherein when a link is in a partial width mode, the logPHY circuit is to send an early valid indication to the first link layer circuit to enable the first link layer circuit to power up ahead of receipt of a first flit from the logPHY circuit.

9. The apparatus of claim 1 , wherein the logPHY circuit is to receive a retry request from a remote link partner for a first flit, and in response to the retry request, to send an indication to the first link layer circuit to cause the first link layer circuit to send one or more no operation (NOP) flits to the logPHY circuit.

10. The apparatus of claim 1 , further comprising a sideband interface coupled between the first link layer circuit and the logPHY circuit to send data link layer packet (DLLP) information, wherein the logPHY circuit is to insert at least a portion of the DLLP information into a replay flit and send the replay flit with the at least portion of the DLLP information to a remote link partner.

11. At least one non-transitory computer readable storage medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:

receiving, in a logical physical (logPHY) circuit, a flit;

sending, from the logPHY circuit, the flit to a link layer circuit coupled to the logPHY circuit in parallel with checking, in the logPHY circuit, the flit for an error;

detecting, in the logPHY circuit, the error in the flit; and

sending a flit cancel signal to the link layer circuit to cause the link layer circuit to drop the flit.

12. The at least one non-transitory computer readable storage medium of claim 11 , wherein the method further comprises:

correcting, in the logPHY circuit, the error in the flit; and

sending the corrected flit to the link layer circuit.

13. The at least one non-transitory computer readable storage medium of claim 11 , wherein the method further comprises in response to a determination that the error cannot be corrected, sending a retry request to a remote link partner to re-send the flit.

14. The at least one non-transitory computer readable storage medium of claim 11 , wherein the method further comprises sending the flit cancel signal within a predetermined number of cycles following sending the flit to the link layer circuit.

15. An apparatus comprising:

a first link layer circuit to perform link layer functionality for a first communication protocol;

a second link layer circuit to perform link layer functionality for a second communication protocol;

a selection circuit coupled to the first link layer circuit and the second link layer circuit, to provide first information from the first link layer circuit to a logical physical (logPHY) circuit and second information from the second link layer circuit to the logPHY circuit; and

the logPHY circuit coupled to the selection circuit, wherein the logPHY circuit is to communicate with the first link layer circuit in a flit mode in which the first information is communicated in a fixed width size and communicate with the second link layer circuit in a non-flit mode in which the second information is communicated in a variable width size,

wherein when a link is in a partial width mode, the logPHY circuit is to send an early valid indication to the first link layer circuit to enable the first link layer circuit to power up ahead of receipt of a flit from the logPHY circuit.

16. The apparatus of claim 15 , wherein the first link layer circuit is to start a flit header in a middle of an output flit and send the output flit with the flit header to the logPHY circuit.

17. The apparatus of claim 15 , wherein the logPHY circuit is to receive a retry request from a remote link partner for a first flit, and in response to the retry request, to send an indication to the first link layer circuit to cause the first link layer circuit to send one or more no operation (NOP) flits to the logPHY circuit.

18. The apparatus of claim 15 , further comprising a sideband interface coupled between the first link layer circuit and the logPHY circuit to send data link layer packet (DLLP) information.

19. The apparatus of claim 18 , wherein the logPHY circuit is to insert at least a portion of the DLLP information into a replay flit and send the replay flit with the at least portion of the DLLP information to a remote link partner.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 5, 2022
From: CHOUDHARY, SWADESH; DAS SHARMA, DEBENDRA
To: CORPORATION, INTEL
Reel/Frame 058554/0462 →
EMPLOYMENT AGREEMENT Recorded Jan 5, 2022
From: WAGH, MAHESH
To: CORPORATION, INTEL
Reel/Frame 058570/0962 →
Continuity (2)
Provisional Application 63137045 · Jan 13, 2021
Related Publication 20210232520A1 · Jul 29, 2021
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