IP Library Granted Patent US 12,093,547
Granted Patent B2
US 12,093,547 · App. 17/231,893 · Granted Sep 17, 2024

User configurable SLC memory size

Inventors: Chace A. Clark (Hillsboro, OR); Francis Corrado (Redwood City, CA)
Assignee: SK hynix NAND Product Solutions Corp.
G06F3/064G06F3/0605G06F3/0629G06F3/0659G06F3/0679
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Quick Facts
Patent No.
US 12,093,547
App. No.
17/231,893
Granted
Sep 17, 2024
Kind
B2
Abstract

An embodiment of an electronic apparatus may include one or more substrates; and a controller coupled to the one or more substrates, the controller including logic to control access to a NAND-based storage media that includes a first cell region with a first number of levels and a second region with a second number of levels that is different from the first number of levels, determine logical block address locations that correspond to a user configurable capacity placeholder, and adjust respective sizes of the first cell region and the second cell region at runtime based on the logical block address locations. Other embodiments are disclosed and claimed.

Claims (47)

1. An electronic apparatus, comprising:

one or more substrates; and

a controller coupled to the one or more substrates, the controller including logic to:

control access to a NAND-based storage media that includes a first cell region with a first number of levels and a second cell region with a second number of levels that is different from the first number of levels,

determine logical block address locations that correspond to a user configurable capacity placeholder, and

adjust respective sizes of the first cell region and the second cell region at runtime based on the logical block address locations.

2. The apparatus of claim 1 , wherein the logic is further to:

enable a feature for user configuration of a size of the first cell region in response to command.

3. The apparatus of claim 2 , wherein the logic is further to:

reserve a range of logical block addresses for management of conversions of capacity between the first cell region and the second cell region.

4. The apparatus of claim 2 , wherein the logic is further to:

preserve user data on the NAND-based storage media when the feature is enabled.

5. The apparatus of claim 4 , wherein the logic is further to:

convert a block of the second cell region into a block of the first cell region.

6. The apparatus of claim 5 , wherein the logic is further to:

move data from the second cell region into the converted block of the first cell region.

7. The apparatus of claim 1 , wherein the controller and the NAND-based storage media are incorporated in a solid-state drive.

8. An electronic storage system, comprising:

NAND-based storage media that includes a first cell region with a first number of levels and a second cell region with a second number of levels that is different from the first number of levels; and

a controller communicatively coupled to the NAND-based storage media, the controller including logic to:

determine logical block address locations that correspond to a user configurable capacity placeholder, and

adjust respective sizes of the first cell region and the second cell region at runtime based on the logical block address locations.

9. The system of claim 8 , wherein the logic is further to:

enable a feature for user configuration of a size of the first cell region in response to command.

10. The system of claim 9 , wherein the logic is further to:

reserve a range of logical block addresses for management of conversions of capacity between the first cell region and the second cell region.

11. The system of claim 9 , wherein the logic is further to:

preserve user data on the NAND-based storage media when the feature is enabled.

12. The system of claim 11 , wherein the logic is further to:

convert a block of the second cell region into a block of the first cell region.

13. The system of claim 12 , wherein the logic is further to:

move data from the second cell region into the converted block of the first cell region.

14. The system of claim 8 , wherein the controller and the NAND-based storage media are incorporated in a solid-state drive.

15. A method of controlling storage, comprising:

controlling access to a NAND-based storage media that includes a first cell region with a first number of levels and a second cell region with a second number of levels that is different from the first number of levels;

determining logical block address locations that correspond to a user configurable capacity placeholder, and

adjusting respective sizes of the first cell region and the second cell region at runtime based on the logical block address locations.

16. The method of claim 15 , further comprising:

enabling a feature for user configuration of a size of the first cell region in response to command.

17. The method of claim 16 , further comprising:

reserving a range of logical block addresses for management of conversions of capacity between the first cell region and the second cell region.

18. The method of claim 16 , further comprising:

preserving user data on the NAND-based storage media when the feature is enabled.

19. The method of claim 18 , further comprising:

converting a block of the second cell region into a block of the first cell region.

20. The method of claim 19 , further comprising:

moving data from the second cell region into the converted block of the first cell region.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2023
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP.
Reel/Frame 062437/0255 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2021
From: CLARK, CHACE A.; CORRADO, FRANCIS
To: INTEL CORPORATION
Reel/Frame 055935/0348 →
Continuity (1)
Related Publication 20210232313A1 · Jul 29, 2021
Cited By (1)
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