SYSTEM-LEVEL CHOPPING IN COULOMB COUNTER CIRCUIT
A signal processing system may include a sensor readout channel configured to convert an electronic signal into a digital quantity, the sensor readout channel comprising an analog-to-digital converter (ADC) having an input and an output, first outside chopping switches located at the input of the ADC, and second outside chopping switches located at the output of the ADC. The ADC may comprise a memory element, first inside chopping switches located at the input of the memory element, and second inside chopping switches located at the output of the memory element. The first outside chopping switches, the second outside chopping switches, the first inside chopping switches, and the second inside chopping switches may be switched at the same frequency such that the memory element is swapped periodically in synchronization with the first outside chopping switches and second outside chopping switches.
1 . A signal processing system comprising:
a sensor readout channel configured to convert an electronic signal into a digital quantity, the sensor readout channel comprising:
an analog-to-digital converter (ADC) having an input and an output;
first outside chopping switches located at the input of the ADC; and
second outside chopping switches located at the output of the ADC;
wherein the ADC comprises:
a memory element;
first inside chopping switches located at the input of the memory element; and
second inside chopping switches located at the output of the memory element; and
wherein the first outside chopping switches, the second outside chopping switches, the first inside chopping switches, and the second inside chopping switches are switched at the same frequency such that the memory element is swapped periodically in synchronization with the first outside chopping switches and the second outside chopping switches.
2 . The signal processing system of claim 1 , wherein the memory element comprises an integrator.
3 . The signal processing system of claim 1 , further comprising an impedance for converting a sensed physical quantity into the electronic signal.
4 . The signal processing system of claim 3 , wherein:
the electronic signal is a voltage; and
the impedance is a resistor configured to convert an electrical current into the voltage.
5 . The signal processing system of claim 4 , wherein the sensor readout channel further comprises a digital accumulator configured to digitally integrate an ADC output signal generated at the output of the ADC to generate the digital quantity representing a net amount of charge that has flowed through the impedance.
6 . The signal processing system of claim 4 , wherein the digital quantity represents a net amount of charge that has been delivered from a battery coupled to the impedance.
7 . The signal processing system of claim 1 , wherein the ADC is a sigma-delta ADC.
8 . The signal processing system of claim 1 , wherein the ADC comprises:
a second memory element;
third inside chopping switches located at the input of the second memory element; and
fourth inside chopping switches located at the output of the second memory element; and
wherein the first outside chopping switches, the second outside chopping switches, the first inside chopping switches, the second inside chopping switches, the third inside chopping switches, and the fourth inside chopping switches are switched at the same frequency such that the memory element and the second memory element are swapped periodically in synchronization with the first outside chopping switches and second outside chopping switches.
9 . The signal processing system of claim 8 , wherein:
the memory element comprises a first integrator; and
the second memory element comprises a second integrator.
10 . A method comprising, in a system comprising a sensor readout channel configured to convert an electronic signal into a digital quantity, wherein the sensor readout channel includes an analog-to-digital converter (ADC) having an input and an output, first outside chopping switches located at the input of the ADC, and second outside chopping switches located at the output of the ADC, and wherein the ADC includes a memory element, first inside chopping switches located at the input of the memory element, and second inside chopping switches located at the output of the memory element:
switching the first outside chopping switches, the second outside chopping switches, the first inside chopping switches, and the second inside chopping switches at the same frequency such that the memory element is swapped periodically in synchronization with the first outside chopping switches and the second outside chopping switches.
11 . The method of claim 10 , wherein the memory element comprises an integrator.
12 . The method of claim 10 , further comprising converting a sensed physical quantity into the electronic signal with an impedance.
13 . The method of claim 12 , wherein:
the electronic signal is a voltage;
the impedance is a resistor; and
the method further comprises converting an electrical current into the voltage with the resistor.
14 . The method of claim 13 , further comprising digitally integrating, with a digital accumulator of the sensor readout channel, an ADC output signal generated at the output of the ADC to generate the digital quantity representing a net amount of charge that has flowed through the impedance.
15 . The method of claim 13 , wherein the digital quantity represents a net amount of charge that has been delivered from a battery coupled to the impedance.
16 . The method of claim 10 , wherein the ADC is a sigma-delta ADC.
17 . The method of claim 10 , wherein the ADC comprises:
a second memory element;
third inside chopping switches located at the input of the second memory element; and
fourth inside chopping switches located at the output of the second memory element; and
the method comprises switching the first outside chopping switches, the second outside chopping switches, the first inside chopping switches, the second inside chopping switches, the third inside chopping switches, and the fourth inside chopping switches at the same frequency such that the memory element and the second memory element are swapped periodically in synchronization with the first outside chopping switches and second outside chopping switches.
18 . The method of claim 17 , wherein:
the memory element comprises a first integrator; and
the second memory element comprises a second integrator.