Random cut patterning

1. An semiconductor device comprising: a cell having:

a first metal line and a second metal line formed extending in a vertical direction; and

a third metal line and a fourth metal line formed perpendicular to the first metal line and the second metal line by:

forming, using a first patterning technique, a first circular region at one end of the first metal line and a second circular region at one end of the second metal line; and

laterally extending, using a second patterning technique, the first circular region to form the third metal line and the second circular region to form the fourth metal line;

wherein a reference line is defined to extend from a top surface of the third metal line, and wherein a distance between the reference line and a top of the fourth metal line is less than two times a height of the third metal line.

2. The semiconductor device of claim 1 , wherein the first patterning technique comprises ultraviolet mask etching and the second patterning technique comprises directional etching.

3. The semiconductor device of claim 1 , wherein a center-to-center distance between a center of the first circular region to a center of the second circular region is less than 50 nm.

4. The semiconductor device of claim 1 , further comprising:

a substrate;

a backside power distribution network formed underneath the substrate, the backside power distribution network configured to power electrical components; and

a through silicon via coupled to the backside power distribution network, the through silicon via configured to provide power to at least two circuits on a front side of the semiconductor device.

5. The semiconductor device of claim 4 , further comprising forming at least two circuits on the top of the substrate, the at least two circuit receiving power from the through silicon via.

6. The semiconductor of claim 1 , wherein a height of the cell is less than 100 nm.

7. The semiconductor device of claim 1 , wherein a distance between a bottom surface of the fourth metal line and a top surface of the third metal line is less than half of a height of the cell.

8. The semiconductor device of claim 1 , further comprising:

a fifth metal line extending in a vertical direction;

a sixth metal line perpendicular to the fifth metal line, the sixth metal line formed by:

forming, using the first patterning technique, a third circular region located at one end of the fifth metal line; and

laterally extending, using the second patterning technique, the third circular region to form the sixth metal line, and

wherein a distance between a bottom surface of the sixth metal line and a top surface of the fourth metal line is less than half of a height of the cell.

9. The semiconductor device of claim 3 , wherein the center-to-center distance is 40 nm.

10. An semiconductor device comprising:

on a substrate of the semiconductor device, a first metal line and a second metal line extending in a vertical direction; and

on the substrate, a third metal line and a fourth metal line extending in a horizontal direction perpendicular to the first metal line and the second metal line, formed respectively by:

forming, using a first patterning technique, a first circular region located at one end of the first metal line and a second circular region at one end of the second metal line;

laterally extending, using a second patterning technique, the first circular region to the third metal line; and

laterally extending, using the second patterning technique, the second circular region to the fourth metal line; and

a backside power distribution network underneath the substrate, wherein the backside power distribution network is configured to power electrical components.

11. The semiconductor device of claim 10 , wherein electrical signals are routed throughout the semiconductor device using the first metal line, the second metal line, the third metal line, and the fourth metal line.

12. The semiconductor device of claim 10 , wherein the first patterning technique is extreme ultraviolet lithography.

13. The semiconductor device of claim 10 , further comprising:

a through silicon via coupled to the backside power distribution network, wherein the through silicon via is configured to provide power to at least two circuits on a front side of the semiconductor device.

14. The semiconductor device of claim 13 , further comprising:

at least two circuits on top of the substrate, wherein the at least two circuits receive power from the through silicon via.

15. The semiconductor device of claim 10 , wherein the first patterning technique comprises at least one of ultraviolet mask etching and extreme ultraviolet lithography, and wherein the second patterning technique comprises at least one of directional etching and lateral etching.

16. An semiconductor device comprising:

a patterned first circular region at one end of a first metal line; and a patterned second circular region at one end of a second metal line; and

wherein the patterned first circular region extends to a third metal line; wherein the patterned second circular region extends to a fourth metal line; and wherein the third metal line and the fourth metal line extend in a horizontal direction perpendicular to the first metal line and the second metal line; and

a patterned third circular region at one end of a fifth metal line.

17. The semiconductor device of claim 16 , wherein a center-center distance between a center of the first circular region to a center of the second circular region is less than 50 nm.

18. The semiconductor device of claim 16 , wherein the height of the cell is 50 nm.

19. The semiconductor device of claim 16 , wherein the patterned third circular region extends laterally to a sixth metal line perpendicular to the fifth metal line, and wherein a distance between a bottom surface of the sixth metal line and a top surface of the fourth metal line is less than half of a height of a cell.

20. The semiconductor device of claim 19 , wherein the height of the cell is less than 100 nm.