IP Library Granted Patent US 11,777,648
Granted Patent B2
US 11,777,648 · App. 17/234,271 · Granted Oct 3, 2023

Error check-based synchronization and broadcast channel

Inventors: Kyle Jung-Lin Pan (Saint James, NY); Fengjun Xi (San Diego, CA)
Assignee: InterDigital Patent Holdings, Inc.
H04L1/0061H04J11/0073H04J11/0076H04L1/0072H04L5/0053H04L69/324
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,777,648
App. No.
17/234,271
Granted
Oct 3, 2023
Kind
B2
Abstract

Systems, methods, and instrumentalities are disclosed for error check-based synchronization. Physical Broadcast Channel (PBCH) data may be determined. A scrambling (e.g., a first scrambling) of the PBCH data may be scrambled via a sequence (e.g., a first sequence). The first sequence may be based on a cell ID and/or timing information. Error check bits may be attached to the scrambled PBCH data and to the timing information. The error check bits may include one or more cyclic redundancy check (CRC) bits. The scrambled PBCH data, the timing information (e.g., the unscrambled timing information), and/or the attached error check bits may be polar encoded. The polar encoding may result in polar encoded bits. A scrambling (e.g., a second scrambling) of the polar encoded bits may be scrambled via a sequence (e.g., a second sequence). The first sequence and the second sequence may be different. The polar encoded bits may be transmitted.

Claims (23)

1. A wireless transmit/receive unit (WTRU), the WTRU comprising:

a processor configured to:

receive a physical broadcast channel (PBCH) transmission, the PBCH transmission comprising first bits;

descramble the first bits comprised in the PBCH transmission to generate second bits, wherein the first bits are descrambled using a first sequence associated with at least a synchronization signal (SS) block index corresponding to the PBCH transmission;

decode the second bits to generate third bits, wherein the second bits are polar encoded, and the third bits comprise timing information associated with the PBCH transmission, scrambled PBCH payload bits, and cyclic redundancy check bits; and

descramble the scrambled PBCH payload bits to generate PBCH payload bits, wherein the PBCH payload bits are descrambled based on at least the timing information.

2. The WTRU of claim 1 , wherein the first bits are descrambled based on cell information.

3. The WTRU of claim 2 , wherein the cell information is a cell identity.

4. The WTRU of claim 1 , wherein the processor is configured to not descramble the timing information associated with the PBCH transmission or the cyclic redundancy check bits after decoding the second bits.

5. The WTRU of claim 1 , wherein the processor is configured to perform an error check of the timing information associated with the PBCH transmission and the scrambled PBCH payload bits using the cyclic redundancy check bits.

6. The WTRU of claim 1 , wherein the PBCH payload bits comprise frame boundary information and SS block index information.

7. The WTRU of claim 6 , wherein the timing information comprises a subset of a system frame number.

8. A method comprising:

receiving a physical broadcast channel (PBCH) transmission, the PBCH transmission comprising first bits;

descrambling the first bits comprised in the PBCH transmission to generate second bits, wherein the first bits are descrambled using a first sequence associated with at least a synchronization signal (SS) block index corresponding to the PBCH transmission;

decoding second bits to generate third bits, wherein the second bits are polar encoded, and the third bits comprise timing information associated with the PBCH transmission, scrambled PBCH payload bits, and cyclic redundancy check bits; and

descrambling the scrambled PBCH payload bits to generate PBCH payload bits, wherein the PBCH payload bits are descrambled on at least the timing information.

9. The method of claim 8 , wherein the first bits are descrambled based on cell information.

10. The method of claim 9 , wherein the cell information is a cell identity.

11. The method of claim 8 , comprising not descrambling the timing information associated with the PBCH transmission or the cyclic redundancy check bits after decoding the second bits.

12. The method of claim 8 , comprising performing an error check of the timing information associated with the PBCH transmission and the scrambled PBCH payload bits using the cyclic redundancy check bits.

13. The method of claim 8 , wherein the PBCH payload bits comprise frame boundary information and SS block index information.

14. The method of claim 8 , timing information comprises a subset of a system frame number.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2023
From: IDAC HOLDINGS, INC.
To: INTERDIGITAL PATENT HOLDINGS, INC.
Reel/Frame 062527/0562 →
Continuity (5)
Continuation 16473013
Provisional Application 62555908 · Sep 8, 2017
Provisional Application 62500769 · May 3, 2017
Provisional Application 62443038 · Jan 6, 2017
Related Publication 20210242965A1 · Aug 5, 2021