SiC MOSFET and method for manufacturing the same

1. A method of making a silicon carbide (SiC) MOSFET device, the method comprising:

a) providing a base layer having a first doping type, wherein the base layer comprises a SiC semiconductor substrate and an epitaxial layer on the SiC semiconductor substrate;

b) forming a patterned first barrier layer on a first surface of the base layer,

c) forming a source region having the first doping type in the base layer using the patterned first barrier layer as an ion implantation mask to define the source region in the base layer;

d) forming a base region having a second doping type, and forming a contact region having the second doping type, in the base layer;

e) forming a gate structure located at an edge areas of a first surface of the epitaxial layer; and

f) wherein the patterned first barrier layer comprises a first part and a second part, wherein the first part of the patterned first barrier layer comprises a semiconductor layer and a removable layer that is different from the semiconductor layer, and wherein the second part of the patterned first barrier layer only comprises the removable layer.

2. The method of claim 1 , wherein the first part of the patterned first barrier layer is located at an edge area of the first surface of epitaxial layer and the second part of the patterned first barrier layer is located at a middle area of the first surface of epitaxial layer.

3. The method of claim 1 , wherein the first part of the patterned first barrier layer is located at edge areas of the first surface of the base layer, the second part of the patterned first barrier layer is located at a middle area of the first surface of the base layer.

4. The method of claim 1 , wherein prior to forming the patterned first barrier layer, further comprising forming a patterned deposition layer on the first surface of the base layer using a first mask, wherein the patterned deposition layer comprises a first part and a second part.

5. The method of claim 4 , wherein the first part of the patterned deposition layer is located at edge areas of the first surface of the base layer, and the second part of the patterned deposition layer is located at a middle area of the first surface of the base layer.

6. The method of claim 4 , wherein the forming the patterned first barrier layer comprises:

a) forming, by a thermal oxidation process, a first oxide layer on the first surface of the base layer and the patterned deposition layer;

b) etching a portion of the first oxide layer to form the patterned first barrier layer; and

c) wherein, in the thermal oxidation process, the first part of the patterned deposited layer is partially oxidized into the first oxide layer, the second part of the deposition layer is completely oxidized into the first oxide layer, the patterned deposition layer remaining on the first surface of the base layer is configured as the semiconductor layer, and the first oxide layer is configured as the removable layer.

7. The method of claim 6 , wherein the second part of the patterned deposition layer is completely oxidized by controlling a width of the second part of the patterned deposition layer.

8. The method of claim 5 , wherein a width of the second part of the patterned deposition layer is not greater than a length of the channel of the device.

9. The method of claim 4 , wherein the patterned deposition layer comprises polysilicon or amorphous silicon.

10. The method of claim 6 , wherein a difference between width of the first oxide layer formed by oxidizing the first part of the deposition layer, and length of a channel of the device is not greater 5% of the length of a channel of the device.

11. The method of claim 1 , further comprising removing the removable layer of the patterned first barrier layer.

12. The method of claim 11 , wherein the forming the contact region comprises:

a) forming a second oxide layer located on the first surface of the base layer and the semiconductor layer;

b) etching the second oxide layer to form sidewall spacers on side surfaces of the semiconductor layer; and

c) forming the contact region using the semiconductor layer and the sidewall spacers as a second barrier layer.

13. The method of claim 12 , wherein after the forming the contact region, the forming the base region comprises:

a) removing the sidewall spacers; and

b) forming the base region using the semiconductor layer as a third barrier layer.

14. The method of claim 11 , prior to the forming the contact region, the forming the base region comprises forming the base region using the semiconductor layer of the patterned first barrier layer as a third barrier layer.

15. The method of claim 4 , prior to the forming the source region, the forming the base region comprises forming the base region using the patterned deposited layer as a third barrier layer.

16. The method of claim 13 , further comprising removing the semiconductor layer.

17. The method of claim 12 , further comprising removing the semiconductor layer and the sidewall spacers.

18. The method of claim 16 , wherein the forming the gate structure comprises:

a) forming a gate oxide layer on the first surface of the epitaxial layer;

b) forming a patterned gate conductor on the gate oxide layer;

c) depositing an interlayer dielectric on the first surface of the base layer and the gate conductor;

d) etching the interlayer dielectric and the gate oxide layer to form an opening in order to expose a portion of the first surface of the base region and the source region;

e) depositing a metal on the opening and the second surface of the base layer in order to form a source electrode and a drain electrode; and

f) wherein the gate conductor covers a portion of the base region and the source region, and the first surface and the second surface of the base layer are opposite to each other.

19. The method of claim 12 , wherein the second oxide layer is formed by a vapor deposition process.

20. An apparatus formed according to the method of claim 1 .