Semiconductor device containing stress relaxation layer and method of making thereof
A structure includes a first material layer, a second material layer, and a stress relaxation layer having a thickness of 0.5 nm or less between the first material layer and the second material layer.
1. A light emitting diode (LED) structure, comprising:
a semiconductor buffer layer comprising a III-nitride semiconductor material;
an n-doped semiconductor material layer;
a stress relaxation layer having a thickness of 0.5 nm or less having a first surface contacting the semiconductor buffer layer and a second surface contacting the n-doped semiconductor material layer;
an anode contact; and
a reflector,
wherein:
the n-doped semiconductor material layer is located between the anode contact and the stress relaxation layer;
the anode contact is located between the reflector and the n-doped semiconductor material layer, and
the LED structure comprises a sidewall extending continuously in a direction perpendicular to the first surface and the second surface of the stress relaxation layer along an entire thickness of the n-doped semiconductor material layer, an entire thickness of the stress relaxation layer, and at least a portion of a thickness of the semiconductor buffer layer.
2. The LED structure of claim 1 , wherein the stress relaxation layer comprises a dielectric layer.
3. The LED structure of claim 1 , further comprising:
a p-doped semiconductor material layer located between the n-doped semiconductor material layer and the anode contact; and
an active region disposed between the n-doped semiconductor layer and the p-doped semiconductor layer.
4. The LED structure of claim 1 , wherein the n-doped semiconductor material layer comprises a III-nitride semiconductor material.
5. The LED structure of claim 4 , wherein the n-doped semiconductor material layer comprises n-doped gallium nitride.
6. The LED structure of claim 5 , wherein the stress relaxation layer comprises aluminum oxide.
7. The LED structure of claim 5 , wherein the stress relaxation layer comprises silicon nitride.
8. The LED structure of claim 1 , wherein the stress relaxation layer has a thickness of 0.2 nm to 0.5 nm.
9. The LED structure of claim 3 , wherein an area of the reflector is less than an area of the anode contact.
10. The LED structure of claim 3 , further comprising a dielectric material layer located between the anode contact and the reflector,
wherein:
an opening extends through the dielectric material layer; and
the reflector extends through the opening in the dielectric material layer to contact the anode contact.
11. The LED structure of claim 10 , wherein the dielectric material layer and the reflector extend over a sidewall of the LED structure and laterally surround the stress relaxation layer.
12. A method of forming a light emitting diode (LED), comprising:
forming a semiconductor buffer layer comprising a III-nitride semiconductor material;
forming a stress relaxation layer having a thickness of 0.5 nm or less on the semiconductor buffer layer, wherein a first surface of the stress relaxation layer contacts the semiconductor buffer layer;
forming an n-doped semiconductor material layer on the stress relaxation layer, wherein a second surface of the stress relaxation layer contacts the n-doped semiconductor layer;
patterning the n-doped semiconductor material layer, the stress relaxation layer, and the semiconductor buffer layer using an etching process to form a sidewall extending continuously in a direction perpendicular to the first surface and the second surface of the stress relaxation layer along an entire thickness of the n-doped semiconductor material layer, an entire thickness of the stress relaxation layer, and at least a portion of a thickness of the semiconductor buffer layer;
forming an anode contact over the n-doped semiconductor material layer; and
forming a reflector over the anode contact.
13. The method of claim 12 , wherein the stress relaxation layer comprises a dielectric layer.
14. The method of claim 12 , further comprising:
forming an active region over the n-doped semiconductor material layer; and
forming a p-doped semiconductor material layer over the active region, wherein the anode contact is formed over the p-doped semiconductor material layer.
15. The method of claim 12 , wherein the semiconductor buffer layer and the n-doped semiconductor material layer comprise a III-nitride semiconductor material.
16. The method of claim 15 , wherein the semiconductor buffer layer comprises undoped gallium nitride and the n-doped semiconductor material layer comprises n-doped gallium nitride.
17. The method of claim 16 , wherein the stress relaxation layer comprises aluminum oxide.
18. The method of claim 16 , wherein the stress relaxation layer comprises silicon nitride.
19. The method of claim 12 , wherein the stress relaxation layer is grown by atomic layer deposition and the n-doped semiconductor material layer is grown by metal organic chemical vapor deposition without breaking vacuum in a same deposition chamber or in different deposition chambers of a same vacuum cluster tool.