IP Library › Granted Patent US 11,476,320
Granted Patent B2
US 11,476,320 · App. 17/240,776 · Granted Oct 18, 2022

Flat panel LED display

Inventor: Heng Liu (Sunnyvale, CA)
Assignee: V-Finity, Inc.
H01L27/3276G02F1/136295H01L2227/323
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Quick Facts
Patent No.
US 11,476,320
App. No.
17/240,776
Filed
Apr 26, 2021
Granted
Oct 18, 2022
Kind
B2
Art Unit
2871
USPC
349/56
Abstract

A light emitting diode display comprises a first panel, which comprises: a first layer having a substrate a second layer having a plurality of pixel circuits disposed on a first surface of the substrate; a plurality of light emitting diodes electrically connected to the pixel circuits; and a driver circuit communicatively coupled to the pixel circuits by at least one electrically conductive via traveling through the first layer; an edge of the panel having a non-emitting space having a length less than a length of a non-emitting space within the panel.

Claims (26)

1. A light emitting diode display, comprising a first panel, the first panel comprising: a first layer having a substrate; a second layer having a plurality of pixel circuits disposed on a first surface of the substrate; a plurality of light emitting diodes electrically connected to the plurality of pixel circuits; and a driver circuit communicatively coupled to the plurality of pixel circuits by at least one electrically conductive via traveling through the first layer; an edge of the first panel having a first non-emitting space having a length less than a length of a second non-emitting space within the first panel, wherein the at least one electrically conductive via are at least one-pixel distance from the edge of the first panel.

2. The light emitting diode display of claim 1 , wherein the driver circuit is mounted on a second surface of the substrate.

3. The light emitting diode display of claim 1 , wherein the plurality of pixel circuits are active matrix.

4. The light emitting diode display of claim 1 , wherein the plurality of pixel circuits are passive matrix.

5. The light emitting diode display of claim 1 , wherein the substrate includes glass.

6. The light emitting diode display of claim 1 , wherein the substrate includes polyimide.

7. The light emitting diode display of claim 1 , further comprising an interconnect, at least one powerline and a power circuit, wherein the plurality of pixel circuits are connected to the at least one powerline, which is connected to the interconnect by the at least one electrically conductive via, and the power circuit is connected to the interconnect.

8. The light emitting diode display of claim 7 , wherein the interconnect is mounted on a second surface of the substrate.

9. The light emitting diode display of claim 7 , wherein the at least one powerline is mounted on the first surface of the substrate.

10. A method of manufacturing a light emitting diode (LED display, comprising:

providing a substrate with pixel circuitry on a first surface;

forming LED dies over the pixel circuitry;

electrically connecting the LED dies to the pixel circuitry;

creating a through hole via in the substrate;

forming electrical conductive material in the through ole via to connect the pixel circuitry to the LED dies;

forming electrical drive circuitry; and

connecting the electrical drive circuitry to the through hole via that connects to the pixel circuitry;

wherein the through hole via is at least one-pixel distance from an edge of the light emitting diode (LED) display.

11. The method of claim 10 , wherein the electrical drive circuitry is mounted on a second surface of the substrate.

12. The method of claim 10 , wherein the pixel circuitry is active matrix.

13. The method of claim 10 , wherein the pixel circuitry is passive matrix.

14. The method of claim 10 , wherein the substrate includes glass.

15. The method of claim 10 , wherein the substrate includes polyimide.

16. The method of claim 10 , further comprising forming an interconnect, at least one powerline and a power circuit, wherein the pixel circuitry is connected to the at least one powerline, which is connected to the interconnect by the through hole via, and the power circuit is connected to the interconnect.

17. The method of claim 16 , wherein the interconnect is mounted on a second surface of the substrate.

18. The method of claim 16 , wherein the at least one powerline is mounted on the first surface of the substrate.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE APPLICATION NUMBER 60901144 PREVIOUSLY RECORDED AT REEL: 060102 FRAME: 0130. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT . Recorded Jun 17, 2022
From: V-FINITY INTERNATIONAL
To: V-FINITY, INC.
Reel/Frame 060455/0629 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2022
From: V-FINITY INTERNATIONAL
To: V-FINITY INC.
Reel/Frame 060102/0130 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 26, 2021
From: LIU, HENG
To: V-FINITY INTERNATIONAL
Reel/Frame 056044/0243 →
Continuity (4)
Continuation In Part 16923895 · Jul 8, 2020
Provisional Application 62881634 · Aug 1, 2019
Provisional Application 62885425 · Aug 12, 2019
Related Publication 20210249502A1 · Aug 12, 2021