Manufacturing method of semiconductor device and semiconductor device
View Patent ↗The present invention provides a manufacturing method of a semiconductor device and a semiconductor device. A semiconductor device is provided, the semiconductor device includes a substrate, a stacked structure disposed on the substrate, the substrate comprises a cell array region, a peripheral circuit region and a middle region between the cell array region and the peripheral circuit region, a first trench located in the middle region, a second support layer located on an upper surface of the stacked structure, wherein parts of the second support layer is disposed in the first trench, and a capacitor structure located in the cell array region.
1. A semiconductor device, comprising:
a substrate;
a stacked structure disposed on the substrate, the substrate comprises a cell array region, a peripheral circuit region and a middle region between the cell array region and the peripheral circuit region;
a first trench located in the middle region;
a second trench disposed between the first trench and the peripheral circuit region;
a second support layer located on an upper surface of the stacked structure, wherein parts of the second support layer is disposed in the first trench and the second trench to form a first guard ring and a second guard ring in the middle region, wherein the second guard ring structure surrounds the first guard ring structure; and
a capacitor structure located in the cell array region.
2. The semiconductor device of claim 1 , wherein the stacked structure comprises a first support layer, and wherein both the first support structure and the second support layer contact the capacitor structure directly in the cell array region.
3. The semiconductor device of claim 1 , wherein the semiconductor device further comprises an ONONO structure located on the substrate of the peripheral circuit region, and the ONONO structure comprises a first dielectric layer, a first support structure, a second dielectric layer, the second support layer and an oxide layer.
4. The semiconductor device of claim 1 , wherein the capacitor structure comprises a lower electrode, a capacitor dielectric layer and an upper electrode.
5. The semiconductor device of claim 1 , wherein parts of the second support layer disposed in the first trench directly contacts the capacitor structure.
6. The semiconductor device of claim 1 , wherein the second support layer disposed on the upper surface of the stacked structure and the second support layer disposed in the first trench are an integrally formed structure.
7. The semiconductor device of claim 1 , wherein the second support layer disposed in the cell array region, in the peripheral circuit region and in the middle region.
8. A method of forming a semiconductor device, comprising:
forming a substrate;
forming a stacked structure on the substrate, wherein the substrate comprises a cell array region, a peripheral circuit region and an middle region between the cell array region and the peripheral circuit region;
forming a first trench in the middle region;
forming a second trench between the first trench and the peripheral circuit region;
forming a second support layer located on an upper surface of the stacked structure, wherein parts of the second support layer is disposed in the first trench and the second trench to form a first guard ring and a second guard ring in the middle region, wherein the second guard ring structure surrounds the first guard ring structure; and
forming a capacitor structure in the cell array region.
9. The method of claim 8 , wherein the stacked structure comprises a first support layer, and wherein both the first support structure and the second support layer contact the capacitor structure directly in the cell array region.
10. The method of claim 8 , wherein the semiconductor device further comprises an ONONO structure located on the substrate of the peripheral circuit region, and the ONONO structure comprises a first dielectric layer, a first support structure, a second dielectric layer, the second support layer and an oxide layer.
11. The method of claim 8 , wherein the capacitor structure comprises a lower electrode, a capacitor dielectric layer and an upper electrode.
12. The method of claim 8 , wherein parts of the second support layer disposed in the first trench directly contacts the capacitor structure.
13. The method of claim 8 , wherein the second support layer disposed on the upper surface of the stacked structure and the second support layer disposed in the first trench are an integrally formed structure.
14. The method of claim 8 , wherein the second support layer disposed in the cell array region, in the peripheral circuit region and in the middle region simultaneously.