Integrated circuit including standard cells, and method of fabricating the same

1. An integrated circuit comprising:

a substrate including a well including dopants of a first conductivity type;

a first device region on the well, the first device region extending in a first direction parallel to the substrate; and

a first isolation element inside the well, the first isolation element extending in the first direction, the first isolation element including,

a first power rail configured to receive a power source voltage, and

a first doping region between the first power rail and the well, the first doping region configured to transfer the power source voltage from the first power rail to the well, and including dopants of the first conductivity type.

2. The integrated circuit of claim 1 , further comprising:

a second device region on the substrate, the second device region extending in the first direction; and

a second isolation element inside the substrate, the second isolation element apart from the first isolation element and extending in the first direction, the second isolation element including,

a second power rail and configured to receive a ground voltage, and

a second doping region between the second power rail and the substrate, the second doping region configured to transmit the ground voltage from the second power rail to the substrate, the second doping region including dopants of a second conductivity type,

wherein the substrate includes dopants of the second conductivity type.

3. The integrated circuit of claim 1 , further comprising:

a plurality of fins in the first device region;

a source/drain region on the plurality of fins;

a contact on the source/drain region, the contact extending in a direction parallel to the substrate; and

a via contacting the first power rail and extending in a direction perpendicular to the substrate,

wherein the contact and the via connect the source/drain region to the first power rail.

4. The integrated circuit of claim 3 , wherein the contact includes a first contact pattern contacting the source/drain region, and a second contact pattern in contact with the via and located on a layer different from a layer on which the first contact pattern is located.

5. The integrated circuit of claim 3 , wherein the via includes a first via pattern and a second via pattern on the first via pattern.

6. The integrated circuit of claim 5 , wherein the first via pattern contacts the first power rail, and the second via pattern contacts the contact.

7. The integrated circuit of claim 1 , further comprising:

a plurality of nanowires in the first device region;

a source/drain region on the plurality of nanowires;

a contact on the source/drain region, the contact extending in a direction parallel to the substrate; and

a via contacting the first power rail and extending in a direction perpendicular to the substrate,

wherein the contact and the via connect the source/drain region to the first power rail.

8. The integrated circuit of claim 1 , further comprising:

a nanosheet in the first device region;

a source/drain region on the nanosheet;

a contact on the source/drain region, the contact extending in a direction parallel to the substrate; and

a via contacting the first power rail and extending in a direction perpendicular to the substrate,

wherein the contact and the via connect the source/drain region to the first power rail.

9. The integrated circuit of claim 1 , wherein the first power rail includes a material selected from the group including cobalt, tungsten, polysilicon including dopants of the first conductivity type, and silicon germanium.

10. An integrated circuit comprising:

a first standard cell including a first device region and a second device region extending in a first direction and spaced apart from each other, the first standard cell on a substrate;

a first isolation element on a boundary of the first standard cell in a second direction; and

a second isolation element on a boundary of the first standard cell in a reverse direction of the second direction, wherein

the first isolation element includes a first power rail, and

the second isolation element includes a second power rail,

wherein the first power rail and the second power rail are configured to electrically connect to the substrate of the first standard cell.

11. The integrated circuit of claim 10 , further comprising:

a first doping region in contact with a bottom surface of the first power rail and including dopants of a first conductivity type; and

a second doping region in contact with a lower portion of the second power rail and including dopants of a second conductivity type.

12. The integrated circuit of claim 10 , further comprising:

a second standard cell;

a third isolation element on a boundary of the second standard cell in a second direction, the third isolation element including a third power rail;

a fourth isolation element on a boundary of the second standard cell in a reverse direction of the second direction, the fourth isolation element including a fourth power rail, wherein

the third isolation element includes a first device isolation layer and surrounding the third power rail; and

the fourth isolation element includes a second device isolation layer and surrounding the fourth power rail.

13. The integrated circuit of claim 10 , further comprising:

a plurality of first fins formed in the first device region;

a first source/drain region on the plurality of first fins;

a first contact on the first source/drain region and extending in a direction parallel to the substrate;

a first via contacting the first power rail and extending in a direction perpendicular to the substrate;

a plurality of second fins in the second device region;

a second source/drain region on the plurality of second fins;

a second contact on the second source/drain region and extending in a direction parallel to the substrate; and

a second via contacting the second power rail and extending in a direction perpendicular to the substrate,

wherein first contact and the first via connect the first source/drain region to the first power rail, and

the second contact and the second via connect the second source/drain region to the second power rail.

14. The integrated circuit of claim 13 , wherein the first contact extends in the second direction, and

the first contact contacts the first via and the first source/drain region.

15. The integrated circuit of claim 13 , wherein the first contact includes a first contact pattern contacting the first source/drain region, and a second contact pattern contacting the first via and on a different layer from the first contact pattern of the first contact, and

the second contact includes a first contact pattern contacting the second source/drain region, and a second contact pattern contacting the second via and on a different layer from the first contact pattern of the second contact.

16. The integrated circuit of claim 13 , wherein each of the first via and the second via includes a first via pattern and a second via pattern on the first via pattern.

17. The integrated circuit of claim 16 , wherein a width of the first via pattern and a width of the second via pattern are different from each other on the contact surface where the first via pattern and the second via pattern contact each other.

18. The integrated circuit of claim 10 , further comprising:

a plurality of first nanowires in the first device region;

first source/drain region on the plurality of first nanowires;

a first contact on the first source/drain region and extending in a direction parallel to the substrate;

a first via contacting the first power rail and extending in a direction perpendicular to the substrate;

a plurality of second nanowires in the second device region;

a second source/drain region on the plurality of second nanowires;

a second contact on the second source/drain region and extending in a direction parallel to the substrate; and

a second via contacting the second power rail and extending in a direction perpendicular to the substrate,

wherein the first contact and the first via connect the first source/drain region to the first power rail, and

the second contact and the second via connect the second source/drain region to the second power rail.

19. The integrated circuit of claim 10 , further comprising:

a plurality of first nanosheets formed in the first device region;

a first source/drain region on the plurality of first nanosheets;

a first contact on the first source/drain region and extending in a direction parallel to the substrate;

a first via contacting the first power rail and extending in a direction perpendicular to the substrate;

a plurality of second nanosheets in the second device region;

a second source/drain region on the plurality of second nanosheets;

a second contact on the second source/drain region and extending in a direction parallel to the substrate; and

a second via contacting the second power rail and extending in a direction perpendicular to the substrate,

wherein the first contact and the first via connect the first source/drain region to the first power rail, and

the second contact and the second via connect the second source/drain region to the second power rail.

20. An integrated circuit comprising:

a standard cell including a substrate having a well including dopants of a first conductivity type;

a first isolation element extending in a first direction and on a boundary of the standard cell in a second direction, the first isolation element including a first power rail and a first doping region contacting a lower portion of the first power rail and the well; and

a second isolation element extending in the first direction and on a boundary of the standard cell in a reverse direction of the second direction, the second isolation element including a second power rail and a second doping region contacting the second power ail and the substrate;

wherein the standard cell further includes,

a first device region extending in a first direction on the well and including dopants of the first conductivity type,

a second device region on the substrate extending in the first direction and including dopants of a second conductivity type, and

a plurality of gate lines extending is a second direction perpendicular to the first direction and spaced apart from each other in the first direction.