Graphene LHFETS (lateral heterostructure field effect transistors) on SI compatible with CMOS BEOL process

1. A field effect transistor comprising:

a substrate;

a passivation layer on the substrate providing a passivated substrate, wherein the passivation layer is inert to XeF 2 , wherein the passivation layer is on a top, a bottom and sides of the substrate; and

a graphene lateral heterostructure field effect transistor (LHFET) on the passivated substrate.

2. The field effect transistor of claim 1 wherein the graphene lateral heterostructure field effect transistor (LHFET) comprises:

a lateral channel on the passivated substrate, the lateral channel comprising a first graphene section, a second graphene section, and a fluorinated graphene section between the first graphene section and the second graphene section;

a source contact coupled to the first graphene section;

a drain contact coupled to the second graphene section;

a gate electrode over the fluorinated graphene section; and

a gate oxide on the lateral channel and between the gate electrode and the lateral channel for insulating the lateral channel from the gate electrode.

3. The field effect transistor of claim 2 wherein the first graphene section and the second graphene section comprise an n-type doping or a p-type doping.

4. The field effect transistor of claim 1 wherein the substrate comprises Si or SiO 2 .

5. The field effect transistor of claim 1 further comprising:

a CMOS circuit on the substrate, wherein the CMOS circuit is coupled to the graphene lateral heterostructure field effect transistor (LHFET).

6. The field effect transistor of claim 1 wherein the passivation layer comprises HfO 2 or Al 2 O 3 .

7. The field effect transistor of claim 2 wherein the gate oxide comprises HfO 2 .

8. A method for providing a field effect transistor comprising:

providing a substrate;

forming a passivation layer on the substrate to form a passivated substrate, wherein the passivation layer is inert to XeF 2 , wherein the passivation layer is on a top, a bottom and sides of the substrate; and

forming a graphene lateral heterostructure field effect transistor (LHFET) on the passivated substrate.

9. The method of claim 8 wherein forming a graphene lateral heterostructure field effect transistor (LHFET) on the passivated substrate comprises:

transferring or depositing graphene on the passivated substrate;

patterning the graphene to form a graphene mesa; and

fluorinating a section of the graphene mesa.

10. The method of claim 9 further comprising doping the graphene with n-type doping or p-type doping.

11. The method of claim 8 wherein the substrate comprises Si or SiO 2 .

12. The method of claim 8 wherein the passivation layer comprises HfO 2 or Al 2 O 3 .

13. The method of claim 8 wherein the graphene lateral heterostructure field effect transistor (LHFET) comprises:

a lateral channel on the passivated substrate, the lateral channel comprising a first graphene section, a second graphene section, and a fluorinated graphene section between the first graphene section and the second graphene section;

a source contact coupled to the first graphene section;

a drain contact coupled to the second graphene section;

a gate electrode over the fluorinated graphene section; and

a gate oxide on the lateral channel and between the gate electrode and the lateral channel for insulating the lateral channel from the gate electrode.

14. The method of claim 8 , wherein the method is compatible with CMOS back-end-of-line (BEOL) processes.

15. The method of claim 8 ,

wherein the top, bottom, and sides of the substrate include edges of the substrate;

wherein forming the passivation layer on the substrate comprises passivating the substrate on a the top, bottom, and sides with an ALD grown deposition of the passivation layer on the substrate to form the passivated substrate, the passivation layer comprising a dielectric material inert to XeF 2 ;

wherein forming the graphene lateral heterostructure field effect transistor (LHFET) on the passivated substrate comprises:

transferring or depositing graphene over the passivated substrate using a transfer method;

patterning the transferred graphene with photolithography and dry etching to create a graphene mesa;

forming a source contact on a first section of the graphene mesa;

forming a drain contact on a second section of the graphene mesa;

fluorinating with XeF 2 a section of the graphene mesa between the source contact and the drain contact to form a fluorinated graphene section on the graphene mesa between the first section of the graphene mesa and the second section of the graphene mesa;

depositing a gate oxide over the fluorinated graphene section; and

forming a gate electrode over the gate oxide.

16. The method of claim 15 wherein the substrate comprises Si or SiO 2 .

17. The method of claim 15 wherein the dielectric material comprises HfO 2 or Al 2 O 3 .

18. The method of claim 15 further comprising doping the graphene with n-type or p-type doping.

19. The method of claim 15 wherein forming the source contact, the drain contact and the gate electrode each comprises:

depositing Ti;

depositing Pt on the Ti;

depositing Au on the Pt; and

using a lift-off process.

20. The method of claim 15 wherein depositing the gate oxide comprises forming a gate oxide layer on the fluorinated graphene section, wherein the gate oxide layer comprises a HfO 2 layer up to 12 nanometers thick.

21. The method of claim 15 wherein fluorinating with XeF 2 a section of the graphene mesa between the source contact and the drain contact to form a fluorinated graphene section on the graphene mesa between the first section of the graphene mesa and the second section of the graphene mesa comprises:

fluorinating the section of the graphene mesa with XeF 2 for 12 to 24 hours at a temperature;

wherein the temperature may be equal to or greater than 20 degrees centigrade to less than or equal to 100 degrees centigrade.