IP Library › Granted Patent US 11,430,794
Granted Patent B2
US 11,430,794 · App. 17/242,932 · Granted Aug 30, 2022

Method for fabricating semiconductor devices

Inventors: Ho Kyun An (Seoul, KR); Bumsoo Kim (Hwaseong-si, KR)
H01L27/10894H01L21/02247H01L21/02252H01L21/28035H01L21/32H01L21/32155H01L27/10814H01L27/10823H01L27/10876H01L27/10897
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Quick Facts
Patent No.
US 11,430,794
App. No.
17/242,932
Granted
Aug 30, 2022
Kind
B2
Abstract

A method for fabricating a semiconductor device includes providing a substrate including a cell region and a core/peripheral region around the cell region, forming a gate insulating film on the substrate of the core/peripheral region, forming a first conductive film of a first conductive type on the gate insulating film, forming a diffusion blocking film within the first conductive film, the diffusion blocking film being spaced apart from the gate insulating film in a vertical direction, after forming the diffusion blocking film, forming an impurity pattern including impurities within the first conductive film, diffusing the impurities through a heat treatment process to form a second conductive film of a second conductive type and forming a metal gate electrode on the second conductive film, wherein the diffusion blocking film includes helium (He) and/or argon (Ar).

Claims (56)

1. A method for fabricating a semiconductor device, the method comprising:

providing a substrate comprising a cell region and a core/peripheral region around the cell region;

forming a gate insulating film on the core/peripheral region of the substrate;

forming a first conductive film of a first conductive type on the gate insulating film;

forming a diffusion blocking film within the first conductive film, the diffusion blocking film being spaced apart from the gate insulating film in a vertical direction;

after forming the diffusion blocking film, forming an impurity pattern comprising impurities within the first conductive film;

diffusing the impurities through a heat treatment process to form a second conductive film of a second conductive type different from the first conductive type; and

forming a metal gate electrode on the second conductive film,

wherein the diffusion blocking film comprises helium (He) and/or argon (Ar).

2. The method for fabricating the semiconductor device of claim 1 , further comprising:

before forming the first conductive film, nitriding a part of the gate insulating film through a nitrogen plasma treatment process.

3. The method for fabricating the semiconductor device of claim 2 , wherein the nitrogen plasma treatment process comprises a post-nitridation annealing (PNA) process.

4. The method for fabricating the semiconductor device of claim 3 , wherein the post-nitridation annealing process comprises a rapid thermal anneal (RTA) process, a millisecond anneal process, a flash anneal process, and/or a laser anneal process.

5. The method for fabricating the semiconductor device of claim 3 , wherein the post-nitridation annealing process is performed at 900° C. or higher and 1200° C. or lower.

6. The method for fabricating the semiconductor device of claim 1 , wherein the diffusion blocking film is formed using a plasma doping process.

7. The method for fabricating the semiconductor device of claim 6 , wherein the plasma doping process uses a dose of 10 14 or more and 10 17 or less.

8. The method for fabricating the semiconductor device of claim 6 , wherein the plasma doping process uses an implantation energy of 0 kV or more and 10 kV or less.

9. The method for fabricating the semiconductor device of claim 1 , wherein the diffusion blocking film is formed using a beamline ion implantation process.

10. The method for fabricating the semiconductor device of claim 1 , wherein the diffusion blocking film is doped with helium (He).

11. A method for fabricating a semiconductor device, the method comprising:

providing a substrate comprising a cell region and a core/peripheral region around the cell region, wherein the core/peripheral region comprises a first region and a second region;

forming a first gate insulating film on the first region;

forming a second gate insulating film on the second region;

forming a first conductive film on the first gate insulating film;

forming a second conductive film having a first conductive type on the second gate insulating film;

forming a mask film on the first conductive film on the first region;

forming a diffusion blocking film within the second conductive film on the second region, the diffusion blocking film being spaced apart from the second gate insulating film in a vertical direction;

after forming the diffusion blocking film, forming an impurity pattern comprising impurities within the second conductive film on the second region;

diffusing the impurities through a heat treatment process to form a third conductive film of a second conductive type different from the first conductive type on the second region;

removing the mask film;

forming a first metal gate electrode on the first conductive film on the first region; and

forming a second metal gate electrode on the third conductive film on the second region,

wherein the diffusion blocking film comprises helium (He) and/or argon (Ar).

12. The method for fabricating the semiconductor device of claim 11 , further comprising:

before forming the second conductive film, nitriding a part of the second gate insulating film through a nitrogen plasma treatment process.

13. The method for fabricating the semiconductor device of claim 12 , wherein the nitrogen plasma treatment process comprises a post-nitridation annealing (PNA) process.

14. The method for fabricating the semiconductor device of claim 13 , wherein the post-nitridation annealing process comprises a rapid thermal anneal (RTA) process, a millisecond anneal process, a flash anneal process, and/or a laser anneal process.

15. The method for fabricating the semiconductor device of claim 13 , wherein the post-nitridation annealing process is performed at 900° C. or higher and 1200° C. or lower.

16. The method for fabricating the semiconductor device of claim 11 , wherein the diffusion blocking film is formed using a plasma doping process.

17. The method for fabricating the semiconductor device of claim 16 , wherein the plasma doping process uses a dose of 10 14 or more and 10 17 or less.

18. The method for fabricating the semiconductor device of claim 16 , wherein the plasma doping process uses an implantation energy of 0 kV or more and 10 kV or less.

19. The method for fabricating the semiconductor device of claim 11 , wherein the diffusion blocking film is formed using a beamline ion implantation process.

20. A method for fabricating a semiconductor device, the method comprising:

providing a substrate comprising a cell region and a core/peripheral region around the cell region;

forming a gate insulating film on the core/peripheral region;

nitriding a part of the gate insulating film;

forming a first conductive film of a first conductive type on the gate insulating film;

forming a second conductive film on the cell region;

forming a mask film on the second conductive film;

forming a diffusion blocking film within the first conductive film on the core/peripheral region, the diffusion blocking film being spaced apart from the gate insulating film in a vertical direction;

after forming the diffusion blocking film, forming an impurity pattern comprising impurities within the first conductive film on the core/peripheral region;

diffusing the impurities through a heat treatment process to form a third conductive film of a second conductive type different from the first conductive type on the core/peripheral region;

removing the mask film;

forming a first metal gate electrode on the third conductive film on the core/peripheral region; and

forming a second metal gate electrode on the second conductive film on the cell region,

wherein the diffusion blocking film comprises helium (He) and/or argon (Ar).

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2021
From: AN, HO KYUN; KIM, BUMSOO
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 056078/0452 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 28, 2021
From: AN, HO KYUN; KIM, BUMSOO
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 056071/0809 →
Priority Claims (1)
KR 10-2020-0131878 · Oct 13, 2020 · national
Continuity (1)
Related Publication 20220115384A1 · Apr 14, 2022