UE configured for multiplexing HARQ-ACK bits of different priorities in a PUCCH transmission

1. An apparatus for a user equipment (UE) configured for operation in a fifth-generation system (5GS), the apparatus comprising: processing circuitry; and memory,

wherein the processing circuitry is configured to:

decode radio-resource control (RRC) configuration information to configure the UE with a first hybrid-automatic repeat request (HARQ) acknowledgement (ACK) (HARQ-ACK) codebook for first priority HARQ-ACK bits and configure the UE with a second HARQ-ACK codebook for second priority HARQ-ACK bits,

the configuration information indicating a first physical uplink control channel (PUCCH) configuration for a first PUCCH resource for the first HARQ-ACK codebook and a second PUCCH configuration for a second PUCCH resource for the second HARQ-ACK codebook; and

multiplex the first priority HARQ-ACK bits and the second priority HARQ-ACK bits in a PUCCH transmission when the first and second PUCCH resources overlap in time,

wherein the processing circuitry is configured to select a resultant PUCCH resource based on the second PUCCH configuration to multiplex the first priority HARQ-ACK bits and the second priority HARQ-ACK bits when the second priority has a priority index of one and the first priority has a priority index of zero,

wherein when the second PUCCH resource configuration is sub-slot based and the second PUCCH resource has a duration of less than a slot, the resultant PUCCH resource is selected to at least one of:

extend in time beyond the second PUCCH resource to a sub-slot boundary within a slot that includes the second PUCCH resource when the second PUCCH resource ends before the sub-slot boundary; and

extend in frequency beyond a frequency of the second PUCCH resource within the slot,

wherein the memory is configured to store the configuration information.

2. The apparatus of claim 1 , wherein the first priority with the priority index of zero is a low priority (LP) and the second priority with the priority index of one is a high priority (HP).

3. The apparatus of claim 2 , wherein the configuration information includes a priority index ‘0’ to indicate the first priority and a priority index ‘1’ to indicate the second priority.

4. The apparatus of claim 3 , wherein when the first PUCCH resource for the first HARQ-ACK codebook overlaps in time with the second PUCCH resource for the second HARQ-ACK codebook, the processing circuitry is configured to separately encode the first priority HARQ-ACK bits and the second priority HARQ-ACK bits for multiplexing in the resultant PUCCH resource when the second priority is a higher priority than the first priority.

5. The apparatus of claim 4 , wherein when the first PUCCH resource for the first HARQ-ACK codebook does not overlap in time with the second PUCCH resource for the second HARQ-ACK codebook, the processing circuitry is configured to refrain from multiplexing the first priority HARQ-ACK bits and the second priority HARQ-ACK bits in any of the PUCCH resources.

6. The apparatus of claim 4 , wherein the processing circuitry is configured to:

decode a first physical downlink shared channel (PDSCH);

decode a second PDSCH;

generate the first priority HARQ-ACK bits based on the decoding of the first PDSCH; and

generate the second priority HARQ-ACK bits based on the decoding of the second PDSCH.

7. The apparatus of claim 6 , wherein the processing circuitry is configured to decode a downlink (DL) scheduling downlink control information (DCI) format, the DCI format including a field to indicate whether to enable or disable HARQ-ACK codebook multiplexing.

8. The apparatus of claim 6 , wherein the first priority with the priority index of zero is a lower priority than the second priority with the priority index of one.

9. The apparatus of claim 6 , wherein the second priority with the priority index of one is a higher priority than the first priority with the priority index of zero.

10. The apparatus of claim 4 , wherein when the first PUCCH resource for the first HARQ-ACK codebook overlaps with the second PUCCH resource for the second HARQ-ACK codebook, to multiplex the first priority HARQ-ACK bits and the second priority HARQ-ACK bits when the second priority is a higher priority than the first priority, the processing circuitry is configured to encode the second priority HARQ-ACK bits for transmission in a first portion of the resultant PUCCH resource and encode the first priority HARQ-ACK bits for transmission in a second portion of the resultant PUCCH resource.

11. The apparatus of claim 4 , wherein the processing circuitry comprises a baseband processor and is configured to:

decode first data received via a first physical downlink shared channel (PDSCH);

decode second data received via a second PDSCH;

generate the first priority HARQ-ACK bits based on the decoding of the first data; and

generate the second priority HARQ-ACK bits based on the decoding of the second data.

12. A non-transitory computer-readable storage medium that stores instructions for execution by processing circuitry of a user equipment (UE) configured for operation in a fifth-generation system (5GS),

wherein the processing circuitry is configured to:

decode radio-resource control (RRC) configuration information to configure the UE with a first hybrid-automatic repeat request (HARQ) acknowledgement (ACK) (HARQ-ACK) codebook for first priority HARQ-ACK bits and configure the UE with a second HARQ-ACK codebook for second priority HARQ-ACK bits,

the configuration information indicating a first physical uplink control channel (PUCCH) configuration for a first PUCCH resource for the first HARQ-ACK codebook and a second PUCCH configuration for a second PUCCH resource for the second HARQ-ACK codebook; and

multiplex the first priority HARQ-ACK bits and the second priority HARQ-ACK bits in a PUCCH transmission when the first and second PUCCH resources,

wherein the processing circuitry is configured to select a resultant PUCCH resource based on the second PUCCH configuration to multiplex the first priority HARQ-ACK bits and the second priority HARQ-ACK bits when the second priority has a priority index of one and the first priority has a priority index of zero,

wherein when the second PUCCH resource configuration is sub-slot based and the second PUCCH resource has a duration of less than a slot, the resultant PUCCH resource is selected to at least one of:

extend in time beyond the second PUCCH resource to a sub-slot boundary within a slot that includes the second PUCCH resource when the second PUCCH resource ends before the sub-slot boundary; and

extend in frequency beyond a frequency of the second PUCCH resource within the slot.

13. The non-transitory computer-readable storage medium of claim 12 , wherein the first priority with the priority index of zero is a low priority (LP) and the second priority with the priority index of one is a high priority (HP).

14. The non-transitory computer-readable storage medium of claim 13 , wherein the configuration information includes a priority index ‘0’ to indicate the first priority and a priority index ‘1’ to indicate the second priority.

15. The non-transitory computer-readable storage medium of claim 14 , wherein when the first PUCCH resource overlaps in time with the second PUCCH resource, the processing circuitry is configured to separately encode the first priority HARQ-ACK bits and the second priority HARQ-ACK bits for multiplexing in the resultant PUCCH resource.

16. The non-transitory computer-readable storage medium of claim 15 , wherein when the first PUCCH resource does not overlap in time with the second PUCCH resource, the processing circuitry is configured to refrain from multiplexing the first priority HARQ-ACK bits and the second priority HARQ-ACK bits in any of the PUCCH resources.

17. The non-transitory computer-readable storage medium of claim 15 , wherein the processing circuitry is configured to:

decode a first physical downlink shared channel (PDSCH);

decode a second PDSCH;

generate the first priority HARQ-ACK bits based on the decoding of the first PDSCH; and

generate the second priority HARQ-ACK bits based on the decoding of the second PDSCH.

18. The non-transitory computer-readable storage medium of claim 17 , wherein the processing circuitry is configured to decode a downlink (DL) scheduling downlink control information (DCI) format, the DCI format including a field to indicate whether to enable or disable HARQ-ACK codebook multiplexing.

19. The non-transitory computer-readable storage medium of claim 17 , wherein the first priority with the priority index of zero is a lower priority than the second priority with the priority index of one.

20. The non-transitory computer-readable storage medium of claim 17 , wherein the second priority with the priority index of one is a higher priority than the first priority with the priority index of zero.

21. The non-transitory computer-readable storage medium of claim 15 , wherein when the first PUCCH resource overlaps with the second PUCCH resource, to multiplex the first priority HARQ-ACK bits and the second priority HARQ-ACK bits when the second priority is a higher priority than the first priority, the processing circuitry is configured to encode the second priority HARQ-ACK bits for transmission in a first portion of the resultant PUCCH resource and encode the first priority HARQ-ACK bits for transmission in a second portion of the resultant PUCCH resource.

22. The non-transitory computer-readable storage medium of claim 15 , wherein the processing circuitry comprises a baseband processor and is configured to:

decode first data receive via a first physical downlink shared channel (PDSCH);

decode second data received via a second PDSCH;

generate the first priority HARQ-ACK bits based on the decoding of the first data; and

generate the second priority HARQ-ACK bits based on the decoding of the second data.

23. An apparatus of a generation node B (gNB) configured for operation in a fifth-generation system (5GS), the apparatus comprising: processing circuitry; and memory,

wherein the processing circuitry is configured to:

encode radio-resource control (RRC) configuration information to configure a user equipment (UE) with a first hybrid-automatic repeat request (HARQ) acknowledgement (ACK) (HARQ-ACK) codebook for first priority HARQ-ACK bits and to configure the UE with a second HARQ-ACK codebook for second priority HARQ-ACK bits, the configuration information indicating a first physical uplink control channel (PUCCH) configuration for a first PUCCH resource for the first HARQ-ACK codebook and a second PUCCH configuration for a second PUCCH resource for the second HARQ-ACK codebook;

decode a PUCCH transmission comprising the first priority HARQ-ACK bits and the second priority HARQ-ACK bits, the first priority HARQ-ACK bits and the second priority HARQ-ACK bits multiplexed in the PUCCH transmission when the first and second PUCCH resources overlap in time,

wherein the processing circuitry is configured to decode the PUCCH transmission received on a resultant PUCCH resource based on the second PUCCH configuration when the second priority has a priority index of one and the first priority has a priority index of zero,

wherein when the second PUCCH resource configuration is sub-slot based and the second PUCCH resource has a duration of less than a slot, the resultant PUCCH resource is at least one of:

extended in time beyond the second PUCCH resource to a sub-slot boundary within a slot that includes the second PUCCH resource when the second PUCCH resource ends before the sub-slot boundary; and

extended in frequency beyond a frequency of the second PUCCH resource within the slot, and

wherein the memory is configured to store the configuration information.

24. The apparatus of claim 23 , wherein when the first PUCCH resource overlaps in time with the second PUCCH resource, the processing circuitry is configured to separately decode the first priority HARQ-ACK bits and the second priority HARQ-ACK bits that are multiplexed in the resultant PUCCH resource when the second priority is a higher priority than the first priority.

25. The apparatus of claim 24 , wherein the processing circuitry is configured to:

encode a first physical downlink shared channel (PDSCH) for transmission to the UE; and

encode a second PDSCH for transmission to the UE,

wherein the first priority HARQ-ACK bits are based on the decoding of the first PDSCH by the UE, and

wherein the second priority HARQ-ACK bits are based on the decoding of the second PDSCH by the UE.