IP Library › Granted Patent US 11,818,899
Granted Patent B2
US 11,818,899 · App. 17/244,212 · Granted Nov 14, 2023

Semiconductor device including layers with different chalcogen compounds and semiconductor apparatus including the same

Inventors: Wooyoung Yang (Suwon-si, KR); Bonwon Koo (Suwon-si, KR); Chungman Kim (Suwon-si, KR); Kwangmin Park (Seoul, KR); Hajun Sung (Hwaseong-si, KR); Dongho Ahn (Hwaseong-si, KR); Changseung Lee (Yongin-si, KR); Minwoo Choi (Hwaseong-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H10B63/24G11C13/0004H10B61/10H10B63/84H10N50/01H10N50/80H10N70/063H10N70/231H10N70/24H10N70/25H10N70/8413H10N70/8825H10N70/8828H10N70/8833H10N70/8836
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Quick Facts
Patent No.
US 11,818,899
App. No.
17/244,212
Granted
Nov 14, 2023
Kind
B2
Abstract

A chalcogen compound layer exhibiting ovonic threshold switching characteristics, a switching device, a semiconductor device, and/or a semiconductor apparatus including the same are provided. The switching device and/or the semiconductor device may include two or more chalcogen compound layers having different energy band gaps. Alternatively, the switching device and/or semiconductor device may include a chalcogen compound layer having a concentration gradient of an element of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and/or indium (In) in a thickness direction thereof. The switching device and/or a semiconductor device may exhibit stable switching characteristics while having a low off-current value (leakage current value).

Claims (71)

1. A semiconductor device comprising:

a first electrode;

a second electrode separated from the first electrode; and

a first chalcogen compound layer and a second chalcogen compound layer between the first electrode and the second electrode, wherein

the first chalcogen compound layer and the second chalcogen compound layer each independently include a first element selected from the group consisting of germanium (Ge) and tin (Sn) and a second element including one or more selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te), and

the first chalcogen compound layer and the second chalcogen compound layer have different compositions from each other,

wherein an energy band gap of the first chalcogen compound layer is greater than an energy band gap of the second chalcogen compound layer by an amount ranging from 0.1 eV to 1.0 eV.

2. The semiconductor device of claim 1 , wherein the semiconductor device has ovonic threshold switching characteristics.

3. The semiconductor device of claim 1 , wherein the first chalcogen compound layer has a greater energy band gap than the second chalcogen compound layer.

4. The semiconductor device of claim 1 , wherein any one of the first chalcogen compound layer and the second chalcogen compound layer further comprises a third element including one or more selected from the group consisting of arsenic (As), antimony (Sb), silicon (Si), and bismuth (Bi).

5. The semiconductor device of claim 1 , wherein the second chalcogen compound layer further comprises a fourth element including one or more selected from the group consisting of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and indium (In).

6. The semiconductor device of claim 1 , wherein the first chalcogen compound layer further comprises a fifth element including one or more selected from the group consisting of carbon (C), nitrogen (N), oxygen (O), phosphorus (P), and sulfur (S).

7. The semiconductor device of claim 1 , wherein the second chalcogen compound layer comprises a compound represented by Formula 1 or Formula 2 below:

[Formula 1]

A a B b C c

[Formula 2]

A a B b C c D d

wherein, in Formula 1 or Formula 2,

A is the first element,

B is the second element,

C is a third element,

D is a fourth element,

a+b+c=1 in Formula 1, and

a+b+c+d=1 in Formula 2.

8. The semiconductor device of claim 1 , wherein the first chalcogen compound layer comprises a compound represented by one of Formula 1, Formula 3, and Formula 4 below:

[Formula 1]

A a B b C c

[Formula 3]

A a B b

[Formula 4]

A a B b C c E e

wherein, in Formula 1, Formula 3, or Formula 4,

A is the first element,

B is the second element,

C is a third element,

E is a fifth element,

a+b+c=1 in Formula 1,

a+b=1 in Formula 3, and

a+b+c+e=1 in Formula 4.

9. The semiconductor device of claim 1 , wherein a volume ratio the second chalcogen compound layer with respect to the first chalcogen compound layer is an amount ranging from 0.1 to 1.5.

10. The semiconductor device of claim 1 , further comprising:

a third chalcogen compound layer adjacent to the second chalcogen compound layer and separated from the first chalcogen compound layer.

11. The semiconductor device of claim 10 , wherein the third chalcogen compound layer comprises a compound represented by one or more of Formulas 1, 3, and 4:

[Formula 1]

A a B b C c

[Formula 3]

A a B b

[Formula 4]

A a B b C c E e

wherein, in Formula 1, Formula 3, or Formula 4,

A is the first element,

B is the second element,

C is a third element,

E is a fifth element,

a+b+c=1 in Formula 1,

a+b=1 in Formula 3, and

a+b+c+e=1 in Formula 4.

12. The semiconductor device of claim 10 ,

wherein the third chalcogen compound layer has a greater energy band gap than the second chalcogen compound layer.

13. A semiconductor apparatus comprising:

a plurality of first electrode lines on a substrate, parallel to an upper surface of the substrate, and extending in a first direction;

a plurality of second electrode lines on the plurality of first electrode lines, parallel to the upper surface of the substrate, and extending in a second direction that is different from the first direction; and

a first semiconductor device arranged at a crossing point between each of the plurality of first electrode lines and the plurality of second electrode lines, and the first semiconductor device including the semiconductor device of claim 1 .

14. The semiconductor apparatus of claim 13 , further comprising:

a plurality of third electrode lines on the plurality of first electrode lines and the plurality of second electrode lines and the plurality of third electrode lines extending in the first direction; and

a second semiconductor device at a crossing point between each of the plurality of second electrode lines and the plurality of third electrode lines,

wherein the second semiconductor device includes a first electrode, a second electrode separated from the first electrode, and a first chalcogen compound layer and a second chalcogen compound layer between the first electrode and the second electrode, and

wherein the first chalcogen compound layer and the second chalcogen compound layer each independently include a first element selected from the group consisting of germanium (Ge) and tin (Sn) and a second element including one or more selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te), and

the first chalcogen compound layer and the second chalcogen compound layer have different compositions from each other.

15. The semiconductor apparatus of claim 13 , further comprising:

a circuit unit for driving the semiconductor device or performing a computation operation.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2021
From: YANG, WOOYOUNG; KOO, BONWON; KIM, CHUNGMAN; PARK, KWANGMIN; SUNG, HAJUN; AHN, DONGHO; LEE, CHANGSEUNG; CHOI, MINWOO
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 056164/0955 →
Priority Claims (2)
KR 10-2020-0145526 · Nov 3, 2020 · national
KR 10-2021-0001064 · Jan 5, 2021 · national
Continuity (1)
Related Publication 20220140003A1 · May 5, 2022
Cited By (2)
US 12,563,744 US 12,588,218