Semiconductor integrated circuit device
A layout structure of a standard cell using a complementary FET (CFET) is provided. The standard cell includes a first three-dimensional transistor and a second three-dimensional transistor formed above the first transistor in the depth direction, between buried first and second power supply lines. A first contact connects a local interconnect connected to the first transistor and the first power supply line. A second contact connects a local interconnect connected to the second transistor and the second power supply line. The second contact is longer in the depth direction and greater in size in planar view than the first contact.
1. A semiconductor integrated circuit device including a standard cell, the standard cell comprising:
a first power supply line formed in a buried wiring layer, extending in a first direction and supplying a first power supply voltage;
a second power supply line formed in the buried wiring layer, extending in the first direction and supplying a second power supply voltage different from the first power supply voltage;
a first transistor that is a three-dimensional transistor of a first conductivity type lying between the first power supply line and the second power supply line as viewed in plan;
a second transistor that is a three-dimensional transistor of a second conductivity type, formed above the first transistor in a depth direction, lying between the first power supply line and the second power supply line as viewed in plan;
a first local interconnect formed above the buried wiring layer in the depth direction and connected to a first terminal that is to be a source or drain of the first transistor;
a second local interconnect formed above the first local interconnect in the depth direction and connected to a second terminal that is to be a source or drain of the second transistor;
a first contact formed at a position where the first power supply line and the first local interconnect overlap each other as viewed in plan, for connecting the first power supply line and the first local interconnect; and
a second contact formed at a position where the second power supply line and the second local interconnect overlap each other as viewed in plan, for connecting the second power supply line and the second local interconnect,
wherein
the second contact is longer in the depth direction than the first contact and greater in size in planar view than the first contact.
2. The semiconductor integrated circuit device of claim 1 , wherein
the standard cell comprises:
a gate interconnect extending in a second direction that is a direction perpendicular to the first direction as viewed in plan and also extending in the depth direction, the gate interconnect being to be gates of the first and second transistors.
3. The semiconductor integrated circuit device of claim 1 , wherein
channel portions of the first and second transistors have an overlap as viewed in plan.
4. The semiconductor integrated circuit device of claim 1 , wherein
the first and second local interconnects extend in a second direction that is a direction perpendicular to the first direction as viewed in plan.
5. The semiconductor integrated circuit device of claim 4 , wherein
the second contact is longer in the second direction than the first contact.
6. A semiconductor integrated circuit device including a standard cell, the standard cell comprising:
a first power supply line formed in a buried wiring layer, extending in a first direction and supplying a first power supply voltage;
a second power supply line formed in the buried wiring layer, extending in the first direction and supplying a second power supply voltage different from the first power supply voltage;
a first transistor that is a three-dimensional transistor of a first conductivity type lying between the first power supply line and the second power supply line as viewed in plan;
a second transistor that is a three-dimensional transistor of a second conductivity type, formed above the first transistor in a depth direction, lying between the first power supply line and the second power supply line as viewed in plan;
a first local interconnect formed above the buried wiring layer in the depth direction and connected to a first terminal that is to be a source or drain of the first transistor;
a second local interconnect formed above the first local interconnect in the depth direction and connected to a second terminal that is to be a source or drain of the second transistor;
a third local interconnect formed above the first local interconnect in the depth direction and connected to a third terminal that is to be the other of the source and drain of the second transistor;
a first contact formed at a position where the first local interconnect and the third local interconnect overlap each other as viewed in plan, for connecting the first local interconnect and the third local interconnect; and
a second contact formed at a position where the second power supply line and the second local interconnect overlap each other as viewed in plan, for connecting the second power supply line and the second local interconnect,
wherein
the second contact is greater in size in planar view than the first contact.
7. The semiconductor integrated circuit device of claim 6 , wherein
the standard cell comprises:
a gate interconnect extending in a second direction that is a direction perpendicular to the first direction as viewed in plan and also extending in the depth direction, the gate interconnect being to be gates of the first and second transistors.
8. The semiconductor integrated circuit device of claim 6 , wherein
channel portions of the first and second transistors have an overlap as viewed in plan.
9. The semiconductor integrated circuit device of claim 6 , wherein
the first, second, and third local interconnects extend in a second direction that is a direction perpendicular to the first direction as viewed in plan.
10. The semiconductor integrated circuit device of claim 9 , wherein
the second contact is longer in the second direction than the first contact.
11. A semiconductor integrated circuit device including a standard cell, the standard cell comprising:
a first power supply line formed in a buried wiring layer, extending in a first direction and supplying a first power supply voltage;
a second power supply line formed in the buried wiring layer, extending in the first direction and supplying the first power supply voltage;
a third power supply line formed in the buried wiring layer, extending in the first direction between the first power supply line and the second power supply line and supplying a second power supply voltage different from the first power supply voltage;
a first transistor that is a three-dimensional transistor of a first conductivity type lying between the first power supply line and the second power supply line as viewed in plan;
a second transistor that is a three-dimensional transistor of a second conductivity type, formed above the first transistor in a depth direction, lying between the first power supply line and the second power supply line as viewed in plan;
a first local interconnect formed above the buried wiring layer in the depth direction and connected to a first terminal that is to be a source or drain of the first transistor;
a second local interconnect formed above the buried wiring layer in the depth direction and connected to a second terminal that is to be a source or drain of the second transistor;
a first contact formed at a position where the first power supply line and the first local interconnect overlap each other as viewed in plan, for connecting the first power supply line and the first local interconnect; and
a second contact formed at a position where the third power supply line and the second local interconnect overlap each other as viewed in plan, for connecting the third power supply line and the second local interconnect,
wherein
the second contact is longer in the depth direction than the first contact and greater in size in planar view than the first contact.
12. The semiconductor integrated circuit device of claim 11 , wherein
the standard cell comprises:
a gate interconnect extending in a second direction that is a direction perpendicular to the first direction as viewed in plan and also extending in the depth direction, the gate interconnect being to be gates of the first and second transistors.
13. The semiconductor integrated circuit device of claim 11 , wherein
channel portions of the first and second transistors have an overlap as viewed in plan.
14. The semiconductor integrated circuit device of claim 11 , wherein
the first and second local interconnects extend in a second direction that is a direction perpendicular to the first direction as viewed in plan.
15. The semiconductor integrated circuit device of claim 14 , wherein
the second contact is longer in the second direction than the first contact.