Display device
A display device includes a light emitting diode electrically connected between a driving voltage line and a common voltage line; a driving transistor electrically connected between the driving voltage line and the light emitting diode; a second transistor electrically connected between a first electrode of the driving transistor electrically connected to the driving voltage line and a data line; a first scan line electrically connected to a gate electrode of the second transistor; a third transistor electrically connected between a second electrode of the driving transistor electrically connected to the light emitting diode and a gate electrode of the driving transistor; and a connection electrode that connects the gate electrode of the driving transistor and the third transistor, wherein at least a part of a contact portion where the connection electrode contacts the third transistor does not overlap the first scan line.
1. A display device comprising:
a light emitting diode electrically connected between a driving voltage line that applies a driving voltage and a common voltage line that applies a common voltage;
a driving transistor electrically connected between the driving voltage line and the light emitting diode;
a second transistor electrically connected between a first electrode of the driving transistor electrically connected to the driving voltage line and a data line that applies a data voltage;
a first scan line electrically connected to a gate electrode of the second transistor;
a third transistor electrically connected between a second electrode of the driving transistor electrically connected to the light emitting diode and a gate electrode of the driving transistor;
a connection electrode that electrically connects the gate electrode of the driving transistor and the third transistor; and
a contact portion where the connection electrode electrically contacts the third transistor,
wherein at least a part of the contact portion does not overlap the first scan line.
2. The display device of claim 1 , wherein the contact portion does not overlap the first scan line.
3. The display device of claim 2 , wherein the third transistor includes:
a first electrode electrically connected to a first electrode of the driving transistor;
a second electrode electrically connected to the connection electrode;
a channel disposed between the first electrode and the second electrode; and
a gate electrode overlapping the channel, and
the second electrode of the third transistor overlaps the connection electrode.
4. The display device of claim 3 , further comprising
an insulating layer disposed between the second electrode of the third transistor and the connection electrode, wherein
the insulating layer includes an opening overlapping the second electrode of the third transistor and the connection electrode,
the second electrode of the third transistor is electrically connected to the connection electrode through the opening, and
the opening does not overlap the first scan line.
5. The display device of claim 4 , wherein the contact portion is disposed in the opening.
6. The display device of claim 4 , further comprising:
a second scan line electrically connected to the gate electrode of the third transistor,
wherein the opening is disposed between the first scan line and the second scan line in a plan view.
7. The display device of claim 6 , wherein a side edge of the opening corresponds to a side edge of the first scan line.
8. The display device of claim 7 , wherein the connection electrode overlaps the first scan line.
9. The display device of claim 6 , wherein the opening is separated from the first scan line.
10. The display device of claim 9 , wherein the connection electrode does not overlap the first scan line.
11. The display device of claim 6 , wherein
the driving transistor and the second transistor include polycrystalline semiconductors and are p-type transistors, and
the third transistor includes an oxide semiconductor and is an n-type transistor.
12. The display device of claim 11 , wherein voltages having opposite polarities are applied to the first scan line and the second scan line, respectively, at a same time.
13. The display device of claim 3 , further comprising:
a boost capacitor electrically connected between the gate electrode of the second transistor and the second electrode of the third transistor,
wherein the contact portion does not overlap the boost capacitor.
14. The display device of claim 1 , wherein
the contact portion includes a first part that overlaps the first scan line, and a second part that does not overlap the first scan line, and
the second part is a remaining area of the contact portion other than the first part.
15. The display device of claim 14 , wherein
the third transistor includes:
a first electrode electrically connected to the first electrode of the driving transistor;
a second electrode electrically connected to the connection electrode;
a channel disposed between the first electrode and the second electrode; and
a gate electrode overlapping the channel, and
the second electrode of the third transistor overlaps the connection electrode.
16. The display device of claim 15 , further comprising:
an insulating layer disposed between the second electrode of the third transistor and the connection electrode, wherein
the insulating layer includes an opening overlapping the second electrode of the third transistor and the connection electrode,
the second electrode of the third transistor is electrically connected to the connection electrode through the opening, and
the opening includes a first part that overlaps the first scan line, and a second part that does not overlap the first scan line, the second part being a remaining portion of the opening other than the first part.
17. The display device of claim 16 , wherein the contact portion is disposed in the opening.
18. A display device comprising:
a driving transistor including a first electrode, a channel, and a second electrode and disposed on a substrate, the driving transistor including a polycrystalline semiconductor;
a first gate insulating layer disposed on the first electrode, the channel, and the second electrode of the driving transistor;
a gate electrode of the driving transistor disposed on the first gate insulating layer and overlapping the channel of the driving transistor;
a first scan line disposed on the first gate insulating layer;
a second gate insulating layer disposed on the gate electrode of the driving transistor and the first scan line;
a lower second scan line disposed on the second gate insulating layer;
a first interlayer insulating layer disposed on the lower second scan line;
a third transistor including a first electrode, a channel, and a second electrode, the third transistor being disposed on the first interlayer insulating layer and including an oxide semiconductor;
a third gate insulating layer disposed on the first electrode, the channel, and the second electrode of the third transistor;
a gate electrode of the third transistor disposed on the third gate insulating layer;
a second interlayer insulating layer disposed on the gate electrode of the third transistor;
a connection electrode disposed on the second interlayer insulating layer and electrically connecting the gate electrode of the driving transistor and the second electrode of the third transistor; and
a contact portion where the connection electrode electrically contacts the second electrode of the third transistor,
wherein at least a part of the contact portion does not overlap the lower second scan line.
19. The display device of claim 18 , wherein
the second interlayer insulating layer and the third gate insulating layer include an opening overlapping the connection electrode and the second electrode of the third transistor,
the contact portion is disposed in the opening, and
at least a part of the opening does not overlap the first scan line.
20. The display device of claim 19 , further comprising:
an upper second scan line, the upper second scan line and the gate electrode of the third transistor being integral with each other, wherein
the opening is disposed between the first scan line and the upper second scan line in a plan view, and
the opening does not overlap the upper second scan line.
21. The display device of claim 20 , further comprising:
a second transistor electrically connected to the first scan line, wherein
the driving transistor and the second transistor include polycrystalline semiconductors and are p-type transistors,
the third transistor includes an oxide semiconductor and is an n-type transistor, and
voltages having opposite polarities are applied to the first scan line and the second scan line, respectively, at a same time.
22. The display device of claim 18 , further comprising:
a first boost electrode, the first boost electrode and the first scan line being integral with each other, and
a second boost electrode, the second boost electrode and the second electrode of the third transistor being integral with each other, wherein
the first boost electrode overlaps the second boost electrode with the second gate insulating layer and the first interlayer insulating layer being disposed between the first boost electrode and the second boost electrode to form a boost capacitor, and
at least a part of the contact portion does not overlap the boost capacitor.