Semiconductor device
A semiconductor device includes a semiconductor chip, and an n-system gate divided transistor, where the “n” is not less than 2, that includes n-number of system transistors formed in the semiconductor chip such as to be individually controlled and that is configured such as to generate a single output signal by selective controls of the n-number of system transistors.
1. A semiconductor device comprising:
a semiconductor chip; and
an n-system gate divided transistor, where the “n” is not less than 2, that includes n-number of system transistors formed in the semiconductor chip so as to be individually controlled and that is configured so as to generate a single output current including system currents generated by selective controls of the n-number of system transistors, the n-system gate divided transistor including a parallel circuit including the n-number of system transistors such that the n-number of system transistors are configured so as to be electrically controlled to an ON-state and OFF-state independently of each other; and
a control circuit that is formed in a region different from the gate divided transistor in the semiconductor chip, and that is configured so as to generate n-number of gate signals by which the n-number of system transistors are to be individually controlled,
wherein two or more of the system transistors are individually controlled by the gate signals input from the control circuit, respectively, to be in ON states during a normal operation, and
at least one of the system transistors is controlled by the gate signal input from the control circuit to be in an ON state while at least one of the system transistors is controlled by the gate signal input from the control circuit to be in an OFF state during an active clamp operation.
2. The semiconductor device according to claim 1 ,
wherein the n-system gate divided transistor is configured such that an ON-resistance is to be changed by individual controls of the n-number of system transistors.
3. The semiconductor device according to claim 1 ,
wherein the n-system gate divided transistor is configured such that a channel utilization is to be changed by individual controls of the n-number of system transistors.
4. The semiconductor device according to claim 1 , further comprising:
n-number of gate wirings configured so as to individually transmit gate signals to the n-number of system transistors.
5. The semiconductor device according to claim 1 , further comprising:
a device region that is demarcated in the semiconductor chip;
wherein the n-number of system transistors are collectively formed in the device region and configure the n-system gate divided transistor.
6. The semiconductor device according to claim 1 ,
wherein the n-number of system transistors are each configured with a single unit transistor or a plurality of unit transistors that are systematized as an individual control target.
7. The semiconductor device according to claim 6 ,
wherein the n-number of system transistors are each configured with a parallel circuit that includes the single unit transistor or the plurality of unit transistors.
8. The semiconductor device according to claim 6 ,
wherein the unit transistor has a trench gate structure.
9. The semiconductor device according to claim 8 ,
wherein the trench gate structure has a multiple electrode structure including an upper electrode and a lower electrode each embedded in a gate trench so as to be vertically insulated and separated by an insulator.
10. The semiconductor device according to claim 9 ,
wherein the lower electrode is fixed to a same potential as a potential of the upper electrode.
11. The semiconductor device according to claim 1 ,
wherein the n-system gate divided transistor is configured so as to be controlled with multiple operational modes each consisting of a different ON-resistance.
12. The semiconductor device according to claim 1 ,
wherein the n-system gate divided transistor is configured so as to be controlled with at least three operational modes by selective controls of at least three of the system transistors.
13. The semiconductor device according to claim 1 ,
wherein the n-system gate divided transistor is configured so as to be controlled with at least two operational modes each consisting of a different ON-resistance in at least two operations of an on-transition operation, a normal operation, an off-transition operation, and an active clamp operation.
14. The semiconductor device according to claim 13 ,
wherein the n-system gate divided transistor is to be controlled such that an ON-resistance at the active clamp operation exceeds an ON-resistance at the normal operation.
15. The semiconductor device according to claim 13 ,
wherein the n-system gate divided transistor is to be controlled such that an ON-resistance at the on-transition operation is to be less than an ON-resistance at the normal operation.
16. The semiconductor device according to claim 1 ,
wherein the n-system gate divided transistor includes:
a single main drain that is configured by n-number of electrically connected system drains of the system transistors,
a single main source that is configured by n-number of electrically connected system sources of the system transistors, and
n-number of main gates that are respectively configured by n-number of electrically separated system gates of the system transistors.
17. The semiconductor device according to claim 16 ,
wherein n-number of gate signals from the control circuit that are electrically independent from each other are individually input into the n-number of system gates of the system transistors, respectively.