High voltage semiconductor device including a doped gate electrode
A high voltage semiconductor device includes a semiconductor region of a first conductivity type having a first region and a second region, a first insulation pattern disposed over the first region of the semiconductor region to have a first thickness, a second insulation pattern disposed over the second region of the semiconductor region to have a second thickness greater than the first thickness, and a gate electrode disposed over the first and second insulation patterns to have a step structure over a boundary region between the first and second regions. The gate electrode has a doping profile that a position of a maximum projection range of impurity ions distributed in the gate electrode over the first region is located at substantially the same level as a position of a maximum projection range of impurity ions distributed in the gate electrode over the second region.
1. A method of fabricating a high voltage semiconductor device, the method comprising:
forming a gate pattern over a first region and a second region of a semiconductor region having a first conductivity type, wherein the gate pattern has a stepped surface profile over a boundary region between the first and second regions;
forming a planarized ion implantation buffer layer covering the gate pattern, wherein a thickness of the planarized ion implantation buffer layer over the first region is different from a thickness of the planarized ion implantation buffer layer over the second region; and
implanting impurity ions into the gate pattern using the planarized ion implantation buffer layer as a screen layer to form a gate electrode, and
wherein forming the planarized ion implantation buffer layer includes:
forming an ion implantation buffer layer covering the gate pattern, wherein the ion implantation buffer layer has a stepped surface profile over a boundary region between the first and second regions; and
planarizing the ion implantation buffer layer.
2. The method of claim 1 , further comprising forming a first insulation pattern and a second insulation pattern over the first region and the second region of the semiconductor region, respectively,
wherein the second insulation pattern is formed to be thicker than the first insulation pattern.
3. The method of claim 2 , wherein the first insulation pattern and the second insulation pattern are formed such that bottom surfaces of the first and second insulation patterns are located at substantially the same level as a top surface of the semiconductor region and a top surface of the second insulation pattern is located at a level which is higher than a level of a top surface of the first insulation pattern.
4. The method of claim 2 , wherein the gate pattern is formed over the first insulation pattern and the second insulation pattern.
5. The method of claim 4 , wherein the gate pattern is formed to have a substantially uniform thickness on both of the first and second insulation patterns.
6. The method of claim 4 , wherein the gate pattern is formed such that a top surface of the gate pattern over the second region is located at a level which is higher than a level of a top surface of the gate pattern over the first region.
7. The method of claim 1 , wherein the ion implantation buffer layer having the stepped surface profile is formed such that a top surface of the ion implantation buffer layer over the first region is located at a level higher than a level of a top surface of the gate pattern over the second region.
8. The method of claim 1 , wherein a thickness of the planarized ion implantation buffer layer over the first region is greater than a thickness of the planarized ion implantation buffer layer over the second region.
9. The method of claim 8 , wherein a thickness of the planarized ion implantation buffer layer over the first region and a thickness of the planarized ion implantation buffer layer over the second region are set such that the gate electrode has a doping profile that a position of a maximum projection range of the impurity ions distributed in the gate electrode over the first region is located at substantially the same level as a position of a maximum projection range of the impurity ions distributed in the gate electrode over the second region.
10. The method of claim 1 , wherein the impurity ions are implanted into the gate pattern such that a position of a maximum projection range of the impurity ions is located in a lower portion of the gate electrode over the second region.
11. The method of claim 1 , wherein the top surface of the planarized ion implantation buffer layer over the first region is the same horizontal level as the top surface of the planarized ion implantation buffer layer over the second region.