Trench gate transistors with low-resistance shield and gate interconnects

1. A transistor comprising:

a semiconductor region;

a trench disposed in the semiconductor region;

a gate electrode disposed in an upper portion of the trench, the gate electrode including:

a first gate electrode segment; and

a second gate electrode segment;

a shield electrode having:

a first shield electrode portion disposed in a lower portion of the trench, the first shield electrode portion being disposed below the first gate electrode segment and the second gate electrode segment; and

a second shield electrode portion orthogonally extending from the first shield electrode portion in the lower portion of the trench to the upper portion of the trench, the second shield electrode portion being disposed between the first gate electrode segment and the second gate electrode segment; and

a patterned buried conductor layer, the first gate electrode segment being electrically coupled with the second gate electrode segment via the patterned buried conductor layer.

2. The transistor of claim 1 , further comprising:

a first dielectric layer electrically isolating the first shield electrode portion from the first gate electrode segment, and electrically isolating the first shield electrode portion from the second gate electrode segment; and

a second dielectric layer disposed on an upper surface of the semiconductor region and over the trench, the patterned buried conductor layer being disposed in the second dielectric layer.

3. The transistor of claim 2 , wherein the second dielectric layer includes:

a first interlayer dielectric disposed on the upper surface of the semiconductor region and over the trench, the patterned buried conductor layer being disposed in an etched pattern in the first interlayer dielectric; and

a second interlayer dielectric disposed on the first interlayer dielectric and the patterned buried conductor layer.

4. The transistor of claim 2 , further comprising:

a signal metal layer coupled with a source terminal of the transistor; and

an electrical contact electrically coupling the signal metal layer to the second shield electrode portion, the electrical contact being electrically insulated from the patterned buried conductor layer by the second dielectric layer.

5. The transistor of claim 1 , further comprising:

a first electrical contact electrically coupling the patterned buried conductor layer to the first gate electrode segment; and

a second electrical contact electrically coupling the patterned buried conductor layer to the second gate electrode segment.

6. The transistor of claim 1 , wherein a portion of the patterned buried conductor layer is arranged in parallel with the trench, the portion of the patterned buried conductor layer being laterally spaced away from the trench.

7. The transistor of claim 1 , wherein the patterned buried conductor layer includes one or more of a metal, a metal silicide, or doped polysilicon.

8. The transistor of claim 1 , wherein the patterned buried conductor layer is formed from a single conductive material layer.

9. A transistor comprising:

a semiconductor region;

a first active region disposed in the semiconductor region, the first active region including a first active segment of the transistor;

a first gate contact region disposed in the semiconductor region and adjacent to the first active region;

a first isolation region disposed in the semiconductor region and adjacent to the first gate contact region, the first gate contact region being disposed between the first active region and the first isolation region;

a shield contact region disposed in the semiconductor region and adjacent to the first isolation region, the first isolation region being disposed between the first gate contact region and the shield contact region;

a second isolation region disposed in the semiconductor region and adjacent to the shield contact region, the shield contact region being disposed between the first isolation region and the second isolation region;

a second gate contact region disposed in the semiconductor region and adjacent to the second isolation region, the second isolation region being disposed between the shield contact region and the second isolation region;

a second active region disposed in the semiconductor region, the second gate contact region being disposed between the second isolation region and the second active region, the second active region including a second active segment of the transistor;

a trench disposed in the semiconductor region, the trench extending from the first active region to the second active region;

a gate electrode disposed in an upper portion of the trench, the gate electrode including:

a first gate electrode segment; and

a second gate electrode segment;

a shield electrode having:

a first shield electrode portion disposed in a lower portion of the trench, the first shield electrode portion being disposed below the first gate electrode segment and the second gate electrode segment; and

a second shield electrode portion orthogonally extending from the first shield electrode portion in the lower portion of the trench to the upper portion of the trench, the second shield electrode portion being disposed between the first gate electrode segment and the second gate electrode segment; and

a patterned buried conductor layer, the first gate electrode segment being electrically coupled with the second gate electrode segment via the patterned buried conductor layer.

10. The transistor of claim 9 , wherein:

the first gate electrode segment extends from the first gate contact region to the first active region; and

the second gate electrode segment extends from the second gate contact region to the second active region.

11. The transistor of claim 9 , further comprising:

a first dielectric layer electrically isolating the first shield electrode portion from the first gate electrode segment, and electrically isolating the first shield electrode portion from the second gate electrode segment; and

a second dielectric layer disposed on an upper surface of the semiconductor region and over the trench, the patterned buried conductor layer being disposed in the second dielectric layer.

12. The transistor of claim 11 , wherein the second dielectric layer includes:

a first interlayer dielectric disposed on the upper surface of the semiconductor region and over the trench, the patterned buried conductor layer being disposed in an etched pattern in the first interlayer dielectric; and

a second interlayer dielectric disposed on the first interlayer dielectric and the patterned buried conductor layer.

13. The transistor of claim 11 , further comprising:

a signal metal layer coupled with a source terminal of the transistor; and

an electrical contact electrically coupling the signal metal layer to the second shield electrode portion, the electrical contact being electrically insulated from the patterned buried conductor layer by the second dielectric layer.

14. The transistor of claim 9 , further comprising:

a first electrical contact electrically coupling the patterned buried conductor layer to the first gate electrode segment; and

a second electrical contact electrically coupling the patterned buried conductor layer to the second gate electrode segment.

15. The transistor of claim 9 , wherein a portion of the patterned buried conductor layer is arranged in parallel with the trench, the portion of the patterned buried conductor layer being laterally spaced away from the trench.

16. The transistor of claim 9 , further comprising:

a dielectric material, the dielectric material being:

disposed on the first shield electrode portion;

disposed between the first gate electrode segment and the second shield electrode portion; and

disposed between the second gate electrode segment and the second shield electrode portion,

the dielectric material electrically isolating the shield electrode from the first gate electrode segment and the second gate electrode segment.

17. A method for forming a transistor, the method comprising:

forming a trench in a semiconductor region;

forming a shield electrode in the trench, the shield electrode including:

a first shield electrode portion disposed in a lower portion of the trench; and

a second shield electrode portion orthogonally extending from the first shield electrode portion in the lower portion of the trench to an upper portion of the trench;

forming a gate electrode in the upper portion of the trench, the gate electrode including:

a first gate electrode segment disposed above the first shield electrode portion; and

a second gate electrode segment disposed above the first shield electrode portion, the second shield electrode portion being disposed between the first gate electrode

segment and the second gate electrode segment; and

forming a patterned buried conductor layer, the first gate electrode segment being electrically coupled with the second gate electrode segment via the patterned buried conductor layer.

18. The method of claim 17 , wherein forming the patterned buried conductor layer includes patterning a single conductive material layer.

19. The method of claim 17 , further comprising:

forming a first electrical contact electrically coupling the patterned buried conductor layer to the first gate electrode segment; and

forming a second electrical contact electrically coupling the patterned buried conductor layer to the second gate electrode segment.

20. The method of claim 17 , wherein a portion of the patterned buried conductor layer is arranged in parallel with the trench, the portion of the patterned buried conductor layer being laterally spaced away from the trench.