Trench gate field-effect transistors with drain runner

1. A field-effect transistor (FET) comprising:

a semiconductor region;

a trench disposed in the semiconductor region;

a trench gate disposed in an upper portion of the trench in an active region of the FET;

a conductive runner disposed in a bottom portion of the trench, the conductive runner being electrically coupled with a drain terminal of the FET via an ohmic contact with a heavily doped implant, a portion of the conductive runner being disposed in the active region below the trench gate; and

a dielectric layer disposed in the trench between trench gate and the conductive runner.

2. The FET of claim 1 , wherein the conductive runner includes at least one of:

a metal; or

a metal-silicide.

3. The FET of claim 1 , further comprising:

a first electrical contact to the conductive runner, the first electrical contact extending, in the trench, from a surface of the semiconductor region to the conductive runner;

a second electrical contact to the trench gate, the second electrical contact extending, in the trench, from the surface of the semiconductor region to the trench gate; and

an electrically insulative material disposed on the conductive runner, the electrically insulative material electrically insulating the first electrical contact from the second electrical contact.

4. The FET of claim 3 , wherein, in the trench in the active region, the electrically insulative material is disposed between the trench gate and the conductive runner.

5. The FET of claim 1 , wherein the trench gate includes:

a gate dielectric disposed on a sidewall of the upper portion of the trench;

a polysilicon spacer disposed on the gate dielectric; and

a metal gate electrode disposed on the polysilicon spacer.

6. The FET of claim 1 , further comprising:

a shield dielectric disposed in the trench, the conductive runner being disposed in the shield dielectric.

7. The FET of claim 1 , wherein the semiconductor region is a well region of a first conductivity type,

the FET further comprising:

a first buried well region of a second conductivity type, opposite the first conductivity type, the well region being disposed on the first buried well region of the second conductivity type; and

a second buried well region of the first conductivity type, the first buried well region being disposed on the second buried well region.

8. A field-effect transistor (FET) comprising:

a semiconductor region;

an active region disposed in the semiconductor region;

a gate contact region disposed in the semiconductor region and adjacent to the active region;

an isolation region disposed in the semiconductor region and adjacent to the gate contact region, the gate contact region being disposed between the active region and the isolation region;

a drain contact region disposed in the semiconductor region and adjacent to the isolation region, the isolation region being disposed between the gate contact region and the drain contact region;

a trench disposed in the semiconductor region;

a trench gate disposed in an upper portion of the trench in an active region of the FET;

a conductive runner disposed in a bottom portion of the trench, the conductive runner extending from the active region to the drain contact region, the conductive runner being electrically coupled with a drain terminal of the FET via an ohmic contact with a heavily doped implant; and

dielectric layer disposed in the trench between the trench gate and the conductive runner.

9. The FET of claim 8 , wherein the conductive runner includes at least one of:

a metal; or

a metal-silicide.

10. The FET of claim 8 , wherein the semiconductor region is a well region of a first conductivity type,

the FET further comprising a buried well region of a second conductivity type, opposite the first conductivity type, the well region of the first conductivity type being disposed on the buried well region of the second conductivity type.

11. The FET of claim 10 , wherein the buried well region is a first buried well region,

the FET further comprising a second buried well region of the first conductivity type, the first buried well region being disposed on the second buried well region.

12. The FET of claim 8 , wherein the heavily doped implant is disposed in the semiconductor region below the trench, the heavily doped implant is electrically coupled with the conductive runner and extending from the active region to the drain contact region.

13. The FET of claim 8 , further comprising, in the drain contact region, an electrical contact to the conductive runner, the electrical contact extending, in the trench, from a surface of the semiconductor region to the conductive runner.

14. The FET of claim 8 , further comprising a trench gate extending from the gate contact region to the active region, the trench gate being disposed in an upper portion of the trench, the trench gate including:

a gate dielectric disposed on a sidewall of the upper portion of the trench;

a polysilicon spacer disposed on the gate dielectric; and

a metal gate electrode disposed on the polysilicon spacer.

15. The FET of claim 14 , further comprising, in the active region and the gate contact region, an insulating layer disposed between the metal gate electrode and the conductive runner.

16. The FET of claim 15 , wherein the sidewall of the trench is a first sidewall of the trench, the trench including a second sidewall opposite the first sidewall, the FET further comprising, in the active region:

a shield dielectric disposed on respective lower portions of the first sidewall and the second sidewall,

the conductive runner, the insulating layer, and a portion of metal gate electrode being, in the active region, disposed within the shield dielectric.

17. The FET of claim 8 , further comprising:

in the drain contact region, a first electrical contact to the conductive runner, the first electrical contact extending, in the trench, from a surface of the semiconductor region to the conductive runner;

in the gate contact region, a second electrical contact to a trench gate, the second electrical contact extending, in the trench, from the surface of the semiconductor region to the trench gate; and

in the isolation region, an electrically insulative material disposed on the conductive runner, the electrically insulative material electrically insulating the first electrical contact from the second electrical contact.

18. A method for producing a field-effect transistor (FET) comprising:

forming a trench in a semiconductor region;

forming a conductive runner in a bottom portion of the trench, the conductive runner being electrically coupled with a drain terminal of the FET via an ohmic contact with a heavily doped implant;

forming a dielectric layer disposed on the conductive runner in the trench; and

forming a trench gate in an upper portion of the trench in an active region of the FET, the trench gate being disposed on the dielectric layer, the dielectric layer being disposed between the conductive runner and the trench gate, and a portion of the conductive runner being disposed in the active region below the trench gate.

19. The method of claim 18 , further comprising:

forming an electrically insulative material disposed on the conductive runner;

forming a first electrical contact to the conductive runner, the first electrical contact extending, in the trench, from a surface of the semiconductor region to the conductive runner; and

forming a second electrical contact to the trench gate, the second electrical contact extending, in the trench, from the surface of the semiconductor region to the trench gate, the electrically insulative material electrically insulating the first electrical contact from the second electrical contact.

20. The method of claim 18 , further comprising, prior to forming the conductive runner:

forming a drain implant in the semiconductor region below the trench, the conductive runner being electrically coupled with the drain implant.