System watchdog timer for a data processing system

1. A circuit comprising a system watchdog timer, the system watchdog timer comprising:

an interface circuit adapted to be coupled to a bus having a predetermined protocol;

a timer; and

a controller coupled to said interface circuit and said timer,

wherein:

in response to a startup signal, said controller starts said timer and generates an initial question;

in response to receiving an initial answer and an initial data code from said bus, said interface circuit calculates an expected data code and compares said expected data code to said initial data code;

in response to a mismatch between said expected data code and said initial data code, said interface circuit provides a bus error signal to said bus; and

in response to a match between said expected data code and said initial data code, said interface circuit provides said initial answer and said initial data code to said controller, and said controller subsequently compares said initial answer with said initial question, wherein:

in response to a match between said initial answer and said initial question, said controller resets said timer and stores said initial data code as a subsequent question; and

in response to a mismatch between said initial answer and said initial question, the system watchdog timer performs a remedial action of the circuit.

2. The circuit of claim 1 , wherein said timer has a first period including a closed window and a second period including an open window, wherein:

in response to receiving said initial answer and said initial data code during said first period of said timer, said controller performs said remedial action.

3. The circuit of claim 1 further comprising a power management circuit, wherein said power management circuit and the system watchdog timer are integrated within an integrated circuit package.

4. The circuit of claim 1 , further comprising:

a data processor coupled to the system watchdog timer via said bus,

wherein:

said data processor provides said startup signal and reads said initial question from the system watchdog timer over said bus; and

in response to reading said initial question, said data processor stores said initial question as said initial answer, calculates said initial data code, stores said initial data code as a subsequent answer, and writes said initial answer and said initial data code to the system watchdog timer.

5. The circuit of claim 4 , wherein said data processor, said bus, and the system watchdog timer are combined within an integrated circuit package.

6. The circuit of claim 4 , wherein said data processor is within a first integrated circuit package, the system watchdog timer is within a second integrated circuit package, and said bus couples said first integrated circuit package to said second integrated circuit package.

7. The circuit of claim 4 , wherein said data processor communicates with the system watchdog timer using a packet that includes a corresponding answer, and provides a data code by performing a cyclic redundancy check operation on said packet and appending said data code to said packet, wherein said data processor uses said data code as an answer for a subsequent packet.

8. The circuit of claim 7 , wherein said data processor includes a bus interface circuit, wherein said bus interface circuit performs said CRC operation using a CRC circuit.

9. The circuit of claim 7 , wherein said data processor includes a central processing unit, wherein said central processing unit performs said CRC operation using a software algorithm.

10. The circuit of claim 1 , wherein said controller calculates said expected data code by performing a CRC operation on said initial question.

11. A method of performing a system watchdog operation of a data processing systm using a system watchdog timer comprising:

creating an initial question;

starting a timer of the system watchdog timer;

receiving an initial answer and an initial data code;

calculating an expected data code in response to said initial question;

comparing said initial data code to said expected data code;

in response to a mismatch between said initial data code and said expected data code, generating a bus error signal; and

in response to a match between said initial data code and said expected data code, comparing said initial answer to said initial question, wherein:

in response to a match between said initial answer and said initial question, resetting said timer and storing said initial data code as a subsequent question; and

in response to a mismatch between said initial answer and said initial question, performing a remedial action of the data processing system.

12. The method of claim 11 , further comprising:

reading said initial question in response to said creating and subsequently storing said initial question as said initial answer by a data processor;

calculating said initial data code and subsequently storing said initial data code as a subsequent answer by said data processor; and

writing said initial answer and said initial data code to the system watchdog timer.

13. The method of claim 12 , wherein said calculating said initial data code comprises performing a CRC operation on a packet, said packet including said initial answer, and wherein the method further comprises appending said initial data code to said packet.