Image sensor with active capacitance cancellation circuitry to reduce pixel output settling time
An image sensor may include an array of image pixels arranged in rows and columns. Each column of pixels may be coupled to current source transistors and capacitance cancellation circuitry. The capacitance cancellation circuitry may include capacitors, a common source amplifier transistor, an autozero switch, a switch for selectively deactivating at least one of the capacitors during sample-and-hold reset and sample-and-hold signal operations.
1. An image sensor, comprising:
an image sensor pixel;
a pixel output line coupled to the image sensor pixel;
a current source transistor having a drain terminal coupled to the pixel output line, having a source terminal coupled to a ground line, and having a gate terminal configured to receive a bias voltage;
a cascode transistor having a drain terminal coupled to the pixel output line, having a source terminal coupled to the drain terminal of the current source transistor, and having a gate terminal; and
a common source amplifier transistor having a source terminal coupled to the ground line, having a gate terminal coupled to the source terminal of the cascode transistor, and having a drain terminal coupled to the gate terminal of the cascode transistor.
2. The image sensor of claim 1 , further comprising:
a first capacitor having a first terminal coupled to the drain terminal of the cascode transistor and having a second terminal coupled to the gate terminal of the common source amplifier transistor;
a second capacitor having a first terminal coupled to the source terminal of the cascode transistor and having a second terminal coupled to the gate terminal of the common source amplifier transistor;
a third capacitor having a first terminal coupled to the source terminal of the cascode transistor and having a second terminal;
an enable transistor having a drain terminal coupled to the second terminal of the third capacitor, having a source terminal coupled to the ground line, and having a gate terminal configured to receive an enable signal;
a current source configured to provide a bias current to the common source amplifier transistor; and
an autozero switch coupled in parallel with the second capacitor.
3. The image sensor of claim 2 , further comprising:
a p-channel transistor having a source terminal coupled to the drain terminal of the common source amplifier transistor, a drain terminal coupled to the ground line, and a gate terminal coupled to the pixel output line.
4. The image sensor of claim 1 , further comprising:
a first capacitor having a first terminal coupled to the drain terminal of the cascode transistor and having a second terminal coupled to the gate terminal of the common source amplifier transistor.
5. The image sensor of claim 4 , further comprising:
a second capacitor having a first terminal coupled to the source terminal of the cascode transistor and having a second terminal coupled to the gate terminal of the common source amplifier transistor.
6. The image sensor of claim 5 , wherein:
the first capacitor has a first capacitance;
the second capacitor has a second capacitance; and
the first capacitance is equal to or greater than the second capacitance.
7. The image sensor of claim 6 , wherein the first capacitance is two to five times greater than the second capacitance.
8. The image sensor of claim 5 , further comprising:
an autozero switch having a first terminal coupled to the first terminal of the second capacitor and having a second terminal coupled to the second terminal of the second capacitor.
9. The image sensor of claim 5 , further comprising: a third capacitor having a first terminal coupled to the source terminal of the cascode transistor and having a term second term.
10. The image sensor of claim 9 , further comprising:
an enable transistor configured to switch the third capacitor in and out of use.
11. The image sensor of claim 1 , further comprising:
a current source configured to provide a bias current to the common source amplifier transistor.
12. The image sensor of claim 11 , further comprising:
a sink transistor configured to at least partially receive the bias current from the current source when a voltage on the pixel output line is low.
13. An image sensor, comprising:
an image sensor pixel;
a pixel output line coupled to the image sensor pixel;
a first transistor having a drain terminal coupled to the pixel output line, having a gate terminal, and having a source terminal;
a second transistor having a drain terminal coupled to the source terminal of the first transistor, having a gate terminal configured to receive a bias voltage, and having a source terminal shorted to a ground line; and
a third transistor coupled to the first transistor in a feedback arrangement such that a change in voltage at the drain terminal of the first transistor causes an opposite change in voltage at the source terminal of the first transistor.
14. The image sensor of claim 13 , further comprising:
a first capacitor having a first terminal coupled to the drain terminal of the first transistor and having a second terminal coupled to the gate terminal of the third transistor.
15. The image sensor of claim 14 , further comprising:
a second capacitor having a first terminal coupled to the source terminal of the first transistor and having a second terminal coupled to the gate terminal of the third transistor, wherein the first capacitor has a larger capacitance than the second capacitor.
16. The image sensor of claim 15 , further comprising:
an autozero switch coupled across the second capacitor.
17. The image sensor of claim 15 , further comprising:
a third capacitor coupled to the source terminal of the first transistor, wherein the third capacitor is selectively configured to at least partially cancel a capacitance on the pixel output line.
18. The image sensor of claim 17 , wherein the third capacitor is configured to cancel out 20-80% of the capacitance on the pixel output line.
19. An image sensor, comprising:
an image sensor pixel;
a pixel output line coupled to the image sensor pixel; and
capacitance cancellation circuitry coupled to the pixel output line, wherein the capacitance cancellation circuitry comprises first, second, and third capacitors configured to at least partially cancel a capacitance on the pixel output line.
20. The image sensor of claim 19 , wherein the capacitance cancellation circuitry further comprises:
a common source amplifier transistor having a gate terminal directly coupled to the first and second capacitors; and
an enable transistor configured to switch the third capacitor out of use during sample-and-hold reset operations and during sample-and-hold signal operations.