IP Library Granted Patent US 11,336,848
Granted Patent B1
US 11,336,848 · App. 17/249,430 · Granted May 17, 2022

Image sensors having dielectric relaxation correction circuitry

Inventors: Denver Lloyd (Boise, ID); Manuel H. Innocent (Wezemaal, BE)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H04N5/3651H04N5/3456H04N5/3725
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Quick Facts
Patent No.
US 11,336,848
App. No.
17/249,430
Granted
May 17, 2022
Kind
B1
Abstract

Some image sensors include pixels with capacitors. The capacitor may be used to store charge in the imaging pixel before readout. The capacitor may be a metal-insulator-metal (MIM) capacitor that is susceptible to dielectric relaxation. Dielectric relaxation may cause lag in the signal on the capacitor that impacts the signal on the capacitor during sampling. The image sensor may include dielectric relaxation correction circuitry that leverages the linear relationship between voltage stress and lag signal to correct for dielectric relaxation. The image sensor may include shielded pixels that operate with a similar timing scheme as the imaging pixels in the active array. Measured lag signals from the shielded pixels may be used to correct imaging data.

Claims (34)

1. An image sensor comprising:

an array of imaging pixels that is exposed to incident light in a plurality of frames;

shielded pixels that are shielded from the incident light, wherein each one of the imaging pixels and shielded pixels includes a capacitor, and wherein the shielded pixels are configured to:

obtain a lag signal measurement by applying a first voltage stress of a first magnitude to the capacitor before a first integration time of a first frame; and

obtain a reference measurement by applying a second voltage stress of the first magnitude to the capacitor after a first integration time of a second frame and before a readout for the second frame.

2. The image sensor defined in claim 1 , further comprising:

dielectric relaxation correction circuitry configured to, using the lag signal measurement and the reference measurement, compensate raw pixel data from the array of imaging pixels.

3. The image sensor defined in claim 2 , further comprising:

memory, wherein the raw pixel data is configured to be stored in the memory.

4. The image sensor defined in claim 3 , wherein the dielectric relaxation correction circuitry is configured to compensate the raw pixel data for a given frame using the lag signal measurement, the reference measurement, and the raw pixel data for a previous frame that is stored in the memory.

5. The image sensor defined in claim 2 , further comprising:

a frame buffer, wherein the dielectric relaxation correction circuitry is configured to use the raw pixel data for at least one previous frame when compensating raw pixel data for a given frame.

6. The image sensor defined in claim 1 , wherein applying the first voltage stress comprises applying the first voltage stress during a shutter period.

7. The image sensor defined in claim 1 , wherein each capacitor has a first capacitor plate and wherein applying the first voltage stress to the capacitor comprises adjusting a voltage that is provided to the first capacitor plate.

8. The image sensor defined in claim 1 , wherein the readout for the second frame is a readout of charge on the capacitor.

9. An image sensor comprising:

an array of imaging pixels that is exposed to incident light, wherein each imaging pixel includes a capacitor;

shielded pixels that are shielded from the incident light and that are configured to generate test signals; and

dielectric relaxation correction circuitry configured to, using the test signals, correct raw pixel data from the imaging pixels for lag caused by dielectric relaxation in the capacitors of the imaging pixels.

10. The image sensor defined in claim 9 , wherein the dielectric relaxation correction circuitry is configured to determine a relationship between lag and voltage stress using the test signals.

11. The image sensor defined in claim 9 , wherein each one of the shielded pixels has a respective capacitor with a respective bottom plate coupled to a driver.

12. The image sensor defined in claim 9 , wherein the array of imaging pixels is operated with a first timing scheme that includes a stress time, a float time, and a reset time and wherein the shielded pixels are operated with a second timing scheme that also includes the stress time, the float time, and the reset time.

13. The image sensor defined in claim 9 , wherein the array of imaging pixels is operated with an integration time of a first duration, wherein the shielded pixels generate a test signal while voltage stress is applied to a capacitor in each one of the shielded pixels for a stress time, and wherein the stress time has a second duration.

14. The image sensor defined in claim 13 , wherein the second duration is the same as the first duration.

15. The image sensor defined in claim 13 , wherein the second duration is within a factor of 3 of the first duration.

16. The image sensor defined in claim 9 , wherein each shielded pixel has the same component arrangement as the array of imaging pixels.

17. An image sensor comprising:

an array of imaging pixels that is exposed to incident light, wherein the array of imaging pixels generate raw pixel data;

shielded pixels that are shielded from the incident light;

a frame buffer that is configured to store the raw pixel data from the array of imaging pixels; and

dielectric relaxation correction circuitry configured to, using the raw pixel data from the frame buffer and measurements from the shielded pixels, compensate the raw pixel data from the imaging pixels for lag caused by dielectric relaxation.

18. The image sensor defined in claim 17 , wherein the dielectric relaxation correction circuitry is configured to determine a linear relationship between lag and voltage stress using the measurements from the shielded pixels.

19. The image sensor defined in claim 17 , wherein each one of the shielded pixels has the same component arrangement as the array of imaging pixels.

20. The image sensor defined in claim 17 , wherein each imaging pixel and each shielded pixel includes a capacitor.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 056595, FRAME 0177 Recorded Aug 16, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 064615/0564 →
SECURITY INTEREST Recorded Jun 15, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 056595/0177 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 3, 2021
From: LLOYD, DENVER; INNOCENT, MANUEL H.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 055471/0903 →
Cited By (1)
US 12,501,722