Detrapping electrons to prevent quick charge loss during program verify operations in a memory device

1. A memory device comprising:

a memory array; and

control logic, operatively coupled with the memory array, to perform operations comprising:

initiating a program operation on the memory array, the program operation comprising a program phase and a program verify phase; and

causing a negative voltage signal to be applied to a first selected word line of a block of the memory array after a positive pass voltage signal and one or more program verify voltage signals are applied to the selected word line during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, and wherein the first selected word line is associated with the program operation.

2. The memory device of claim 1 , wherein the negative voltage signal is applied to the first selected word line before a positive pass voltage signal is applied to the first selected word line during the program verify phase of the program operation.

3. The memory device of claim 2 , wherein the program operation comprises a multi-pass program operation comprising a plurality of program phases and a plurality of program verify phases.

4. The memory device of claim 3 , wherein the control logic is to perform operations further comprising:

causing the negative voltage signal to be applied to the first selected word line and to a second word line adjacent to the first selected word line during a first program verify phase of the plurality of program verify phases, wherein the second word line is coupled to a second memory cell of the first plurality of memory cells on a first side of the first memory cell in the string of memory cells.

5. The memory device of claim 4 , wherein the control logic to perform operations further comprising:

causing the negative voltage signal to be applied to the first selected word line and to a third word line adjacent to the first selected word line during a second program verify phase of the plurality of program verify phases, wherein the third word line is coupled to a third memory cell of the first plurality of memory cells on a second side of the first memory cell in the string of memory cells.

6. The memory device of claim 1 , wherein the program operation comprises a plurality of program phases and a plurality of program verify phases, each associated with different programming voltages, and wherein the negative voltage is applied to the first selected word line only during a subset of the plurality of program verify phases associated with programming voltages that exceed a predefined threshold voltage level.

7. A method comprising:

initiating a program operation on a memory array, the program operation comprising a program phase and a program verify phase; and

causing a negative voltage signal to be applied to a first selected word line of a block of the memory array after a positive pass voltage signal and one or more program verify voltage signals are applied to the selected word line during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, and wherein the first selected word line is associated with the program operation.

8. The method of claim 7 , wherein the negative voltage signal is applied to the first selected word line before a positive pass voltage signal is applied to the first selected word line during the program verify phase of the program operation.

9. The method of claim 8 , wherein the program operation comprises a multi-pass program operation comprising a plurality of program phases and a plurality of program verify phases.

10. The method of claim 9 , wherein the control logic is to perform operations further comprising:

causing the negative voltage signal to be applied to the first selected word line and to a second word line adjacent to the first selected word line during a first program verify phase of the plurality of program verify phases, wherein the second word line is coupled to a second memory cell of the first plurality of memory cells on a first side of the first memory cell in the string of memory cells.

11. The method of claim 10 , wherein the control logic to perform operations further comprising:

causing the negative voltage signal to be applied to the first selected word line and to a third word line adjacent to the first selected word line during a second program verify phase of the plurality of program verify phases, wherein the third word line is coupled to a third memory cell of the first plurality of memory cells on a second side of the first memory cell in the string of memory cells.

12. The method of claim 7 , wherein the program operation comprises a plurality of program phases and a plurality of program verify phases, each associated with different programming voltages, and wherein the negative voltage is applied to the first selected word line only during a subset of the plurality of program verify phases associated with programming voltages that exceed a predefined threshold voltage level.

13. A memory device comprising:

a memory array; and

control logic, operatively coupled with the memory array, to perform operations comprising:

receiving a program command corresponding to a program operation on the memory array;

causing a program voltage signal to be applied to a first selected word line of a block of the memory array during a program phase of the program operation to program a corresponding first memory cell in a string of memory cells in the block to a target voltage; and

causing a negative voltage signal to be applied to the first selected word line during a program verify phase of the program operation after a positive pass voltage signal and a program verify signal are applied to the first selected word line to verify that the first memory cell has reached the target voltage.

14. The memory device of claim 13 , wherein the program operation comprises a multi-pass program operation comprising a plurality of program phases and a plurality of program verify phases.

15. The memory device of claim 14 , wherein the control logic is to perform operations further comprising:

causing the negative voltage signal to be applied to the first selected word line and to a second word line adjacent to the first selected word line during a first program verify phase of the plurality of program verify phases, wherein the second word line is coupled to a second memory cell of the first plurality of memory cells on a first side of the first memory cell in the string of memory cells.

16. The memory device of claim 15 , wherein the control logic to perform operations further comprising:

causing the negative voltage signal to be applied to the first selected word line and to a third word line adjacent to the first selected word line during a second program verify phase of the plurality of program verify phases, wherein the third word line is coupled to a third memory cell of the first plurality of memory cells on a second side of the first memory cell in the string of memory cells.

17. The memory device of claim 13 , wherein the program operation comprises a plurality of program phases and a plurality of program verify phases, each associated with different programming voltages, and wherein the negative voltage is applied to the first selected word line only during a subset of the plurality of program verify phases associated with programming voltages that exceed a predefined threshold voltage level.

18. The memory device of claim 13 , wherein the positive pass voltage signal has a higher magnitude than the program verify signal.