Method and system of a power converter with secondary side active clamp

1. A method of operating a power converter, the method comprising:

making a push transistor, on a primary side of the power converter, conductive at a first frequency and a duty cycle during conductive periods, each conductive period of the push transistor defining a push phase of the power converter;

making a pull transistor, on the primary side of the power converter, conductive at the first frequency and the duty cycle during conductive periods, each conductive period of the pull transistor defining a pull phase of the power converter;

adjusting the duty cycle based on a signal indicative of an output voltage;

making a push rectifier, on a secondary side of the power converter, conductive during each push phase, the push rectifier coupled to a phase node on the secondary side of the power converter;

making a pull rectifier, on the secondary side of the power converter, conductive during each pull phase, the pull rectifier coupled to the phase node;

limiting a push-phase voltage excursion of the phase node during the push phase, the limiting the push-phase voltage excursion by:

conducting current from the phase node through a diode to a clamp capacitor for a first duration; and then

conducting current through an electrically-controlled switch for a second duration, the electrically-controlled switch coupled in parallel with the diode; and then

ending the second duration prior to an end of the push phase;

limiting a pull-phase voltage excursion of the phase node during the pull phase, the limiting the pull-phase voltage excursion by extracting current from the phase node and storing the current on the clamp capacitor; and

utilizing the current stored on the clamp capacitor to drive a component on the secondary side.

2. The method of claim 1 wherein extracting current from the phase node during the pull phase further comprises:

conducting current from the phase node through the diode to the clamp capacitor for the first duration; and then

conducting current through the electrically-controlled switch for the second duration.

3. The method of claim 1 wherein utilizing the current stored in the clamp capacitor further comprises utilizing the current in the clamp capacitor to drive the electrically-controlled switch.

4. The method of claim 1 wherein the first duration is a first predetermined time, and wherein the second duration is a second predetermined time.

5. The method of claim 4 wherein extracting current from the phase node during the pull phase further comprises:

conducting current from the phase node through the diode to the clamp capacitor for the first predetermined time; and then

conducting current through the electrically-controlled switch for the second predetermined time.

6. A controller for a power converter, the controller comprising:

a push terminal, a pull terminal, a feedback terminal, and a clamp terminal;

the controller configured to:

assert the push terminal to operate a push transistor on a primary side of the power converter and a push rectifier on a secondary side of the power converter, the assertion of the push terminal at a first frequency, a duty cycle, and a first phase, thereby defining a push phase of the power converter;

assert the pull terminal to operate a pull transistor on the primary side and a pull rectifier on the secondary side, the assertion of the pull terminal at the first frequency, the duty cycle, and a second phase different than the first phase, thereby defining a pull phase of the power converter;

adjust the duty cycle based a feedback signal received on the feedback terminal;

assert the clamp terminal to operate an electrically-controlled switch of a clamp circuit for a first duration during assertion of the push terminal when a voltage on a phase node on the secondary side of the power converter exceeds an excursion voltage; and

refrain from asserting the clamp terminal for a second duration after assertion of the pull terminal during the pull phase, and then assert the clamp terminal for a first predetermined duration when the voltage on the phase node exceeds the excursion voltage during the assertion of the pull terminal, and then de-assert the clamp terminal after the first predetermined duration.

7. The controller of claim 6 wherein when the controller asserts the clamp terminal during assertion of the push terminal, the controller further configured to assert the clamp terminal for a third duration after assertion of the push terminal.

8. The controller of claim 7 wherein, during assertion of the push terminal, the controller is further configured to de-assert the clamp terminal for a second predetermined duration after assertion of the clamp terminal.

9. A power converter, comprising

primary side comprising:

a primary winding of a transformer, the primary winding having a first lead and a second lead;

a push-high transistor having a drain coupled to an input voltage, a source coupled to the first lead, and a gate;

a pull-low transistor having a drain coupled to the first lead, a source coupled to a reference voltage on the primary side, and a gate;

secondary side comprising:

a secondary winding of the transformer, the secondary winding having a third lead and a fourth lead;

an output inductor having a first lead defining a phase node, and a second lead defining an output voltage;

a push rectifier having a drain coupled to the fourth lead, a source coupled to a reference voltage on the secondary side, and a gate; and

a pull rectifier having a drain coupled to the third lead, a source coupled to the reference voltage on the secondary side, and a gate;

a clamp circuit comprising:

a diode having an anode coupled to the phase node and a cathode;

an electrically-controlled switch having a first connection coupled to the phase node, a second connection coupled to the cathode, and control input;

a clamp capacitor having a first lead coupled to the cathode, and a second lead coupled to the reference voltage on the secondary side;

wherein the diode extracts current from the phase node and applies the current to the clamp capacitor when a voltage on the phase node exceeds an excursion voltage; and

a controller configured to:

assert the gate of the push-high transistor at a first frequency and a duty cycle, thereby defining a push phase of the power converter;

assert the gate of the pull-low transistor at the first frequency and the duty cycle, thereby defining a pull phase of the power converter;

assert the gate of the push rectifier at the first frequency during the push phase;

assert the gate of the pull rectifier at the first frequency during the pull phase;

adjust the duty cycle based on a signal indicative of the output voltage;

assert the control input of the electrically-controlled switch for a first duration during the push phase when the voltage on the phase node exceeds the excursion voltage; and

refrain from asserting the control input of the electrically-controlled switch for a second duration after assertion of the gate of the pull-low transistor during the pull phase, and then assert the control input for a first predetermined duration when the voltage on the phase node exceeds the excursion voltage, and then de-assert the control input after the first predetermined duration.

10. The power converter of claim 9 wherein when the controller asserts the control input of the electrically-controlled switch during the push phase, the controller is further configured to:

refrain from asserting the control input for a third duration after assertion of the gate of the push-high transistor; and then

assert the control input for the first duration.

11. The power converter of claim 10 wherein, during the push phase, the controller is further configured to de-assert the control input after a second predetermined duration.

12. The power converter of claim 9 further comprising:

a gate driver circuit defining a power input coupled to the first lead of the clamp capacitor;

the gate driver circuit coupled to the gate of the push rectifier, and a push-high terminal of the controller; and

wherein the gate driver circuit derives power from the clamp capacitor.

13. The power converter of claim 9 wherein the primary side further comprises:

a push-low transistor having a drain coupled to the second lead, a source coupled to the reference voltage on the primary side, and a gate coupled to the controller;

a pull-high transistor having a drain coupled to the input voltage, a source coupled to the second lead, and a gate coupled to the controller;

the controller further configured to:

assert the gate of the push-low transistor at the first frequency and the duty cycle during the push phase; and

assert the gate of the pull-high transistor at the first frequency and the duty cycle during the pull phase.

14. The power converter of claim 9 wherein the secondary side further comprises:

a push-high rectifier having a drain coupled to the phase node, a source coupled to the third lead, and a gate coupled to the controller;

a pull-high rectifier having a drain coupled to the phase node, a source coupled to the fourth lead, and a gate coupled to the controller;

wherein the push rectifier is a push-low rectifier, and the pull rectifier is a pull-low rectifier;

the controller further configured to:

assert the gate of the push-high rectifier at the first frequency and the duty cycle during the push phase; and

assert the gate of the pull-high rectifier at the first frequency and the duty cycle during the pull phase.