Short circuit detection circuit

1. A gate driver with short circuit protection for driving a gate of a first transistor having a drain and a source, comprising:

an inverter having an input for receiving a drain signal from the drain of the first transistor and an output for providing an inverted signal;

a digital processing circuit having a first input coupled to said output of said inverter, a second input for receiving a control signal, and an output for providing a detect signal, wherein said digital processing circuit provides said detect signal in an active logic state in response to said inverted signal and control signal being in respective active states; and

a driver having a first input coupled to said output of said digital processing circuit, a second input for receiving said control signal, and an output for providing a drive signal, wherein said driver provides said drive signal in an active logic state when said control signal is active and said detect signal is inactive, and in an inactive logic state otherwise.

2. The gate driver of claim 1 , wherein said inverter has a programmable switchpoint.

3. The gate driver of claim 2 , further comprising a plurality of fuses coupled to said inverter for determining said programmable switchpoint.

4. The gate driver of claim 1 , wherein said inverter, said digital processing circuit, and said driver are in a first power supply voltage domain.

5. The gate driver of claim 1 , wherein said digital processing circuit comprises:

a logic gate responsive to said inverted signal and said control signal to provide a set signal; and

a latch circuit set in response to said set signal and reset in response to said control signal.

6. The gate driver of claim 5 , wherein:

said latch circuit is set in response to said control signal and said inverted signal being active; and

wherein said latch circuit is reset when said control signal is inactive.

7. The gate driver of claim 6 , wherein said latch circuit is further set in response to said drive signal being active.

8. The gate driver of claim 1 further comprising a second transistor having a drain for receiving said drain signal, a source coupled to said input of said inverter, and a gate coupled to a power supply voltage terminal, wherein said inverter, said digital processing circuit, and said driver are coupled to said power supply voltage terminal.

9. The gate driver of claim 1 wherein said inverter, said digital processing circuit, said driver, and the first transistor are combined in a monolithic integrated circuit.

10. A circuit comprising a switching converter, the switching converter comprising:

a controller for providing a first control signal in response to a feedback signal;

a first driver for providing a first drive signal in response to said first control signal;

a first transistor for conducting a first current into an inductive load in response to said first drive signal, wherein a drain of said first transistor forms a first drain signal; and

a first short circuit detection circuit comprising:

a first inverter for providing a first inverted signal in response to said first drain signal; and

a first digital processing circuit that provides a first detect signal in an active state when said first inverted signal and said first control signal are in respective active states,

wherein said first driver provides said first drive signal in an active logic state when said first control signal is active and said first detect signal is inactive, and in an inactive logic state otherwise.

11. The circuit of claim 10 , wherein said first inverter has a programmable switchpoint.

12. The circuit of claim 11 , wherein said first short circuit detection circuit further comprises a plurality of fuses coupled to said first inverter for determining said programmable switchpoint.

13. The circuit of claim 10 , wherein said first digital processing circuit comprises a logic gate responsive to said first inverted signal and said first control signal to provide a set signal in an active logic state in response to said first inverted signal and said first control signal being active.

14. The circuit of claim 13 , wherein said first digital processing circuit further comprises a latch circuit responsive to said set signal and said first control signal to provide said first detect signal in said active logic state in response to both said set signal and said first control signal being active.

15. The circuit of claim 13 , wherein said logic gate provides said set signal further in response to said first drive signal.

16. The circuit of claim 10 , wherein said controller, said first driver, said first transistor, and said first short circuit detection circuit are combined within a single integrated circuit die.

17. The circuit of claim 10 , wherein said controller provides a second control signal in response to said feedback signal, the switching converter further comprising:

a second driver for providing a second drive signal in response to said second control signal; and

a second transistor for conducting a second current into said inductive load in response to said second drive signal.

18. The circuit of claim 17 , wherein a drain of said second transistor forms a second drain signal, the switching converter further comprising a second short circuit protection circuit comprising:

a second inverter for providing a second inverted signal in response to said second drain signal; and

a second digital processing circuit that provides a second detect signal in an active state when said second inverted signal and said second control signal are in respective active states,

wherein said second driver provides said second drive signal in an active logic state when said second control signal is active and said second detect signal is inactive, and in an inactive logic state otherwise.

19. The circuit of claim 17 further comprising:

an inductor for providing an output voltage in response to said first current and said second current; and

a feedback circuit for providing said feedback signal in response to said output voltage.

20. A method for detecting a short circuit:

driving a transistor in response to a drive signal;

forming a drain signal of said transistor;

generating an inverted signal in response to said drain signal;

generating a detect signal when said inverted signal and a control signal are active; and

providing said drive signal in an active logic state when said control signal is active and said detect signal is inactive, and in an inactive logic state otherwise.

21. The method of claim 20 , wherein said generating said detect signal comprises forming a set signal when said inverted signal and said control signal are active.

22. The method of claim 21 , wherein:

said generating said detect signal further comprises setting a latch ( 220 ) in response to said set signal; and

the method further comprises resetting said latch when said control signal is inactive.

23. The method of claim 21 , wherein said forming said set signal comprises pulsing said set signal when said drive signal is active.

24. The method of claim 20 , wherein said generating said inverted signal comprises using an inverter with a programmable switchpoint, and activating said inverted signal when said drain signal passes said programmable switchpoint.

25. The method of claim 24 , further comprising programming said programmable switchpoint using a plurality of fuses coupled to said inverter.