Signal processing circuit, signal processing device, and signal processing method to suppress power consumption

1. A signal processing circuit, comprising:

a plurality of first circuits each including a first time-length signal output circuit and a second time-length signal output circuit, wherein

the first time-length signal output circuit is configured to output a first time-length signal representing a time length between first timing at which a first input signal changes and second timing at which a second input signal changes, and

the second time-length signal output circuit is configured to output the first time-length signal as a second time-length signal at timing based on a control signal; and

a second circuit configured to output the second time-length signal having the longest time length among a plurality of second time-length signals output respectively from the plurality of first circuits.

2. The signal processing circuit according to claim 1 , wherein

the first time-length signal output circuit is a first logic circuit configured to subject the first input signal and the second input signal to a logic operation.

3. The signal processing circuit according to claim 2 , wherein the first logic circuit is an exclusive disjunction circuit.

4. The signal processing circuit according to claim 1 , wherein

the second time-length signal output circuit has a charge/discharge circuit configured to:

charge an electricity storage element with electric charge based on the first time-length signal; and

discharge the electricity storage element based on the control signal, and

a comparison circuit configured to:

compare a potential of the electricity storage element with a reference potential; and

output the second time-length signal in a period in which the potential of the electricity storage element is equal to or higher than the reference potential.

5. The signal processing circuit according to claim 4 , wherein

the charge/discharge circuit has a capacitor serving as the electricity storage element having a first end electrically connected to the reference potential,

a first constant current source having a first end electrically connected to a first power source potential,

a first switch having an input/output path electrically connected between a second end of the first constant current source and a second end of the capacitor and having a control terminal to which the first time-length signal is supplied,

a second constant current source having a first end electrically connected to a second power source potential, and

a second switch having an input/output path electrically connected between the second end of the capacitor and a second end of the second constant current source and having a control terminal to which the control signal is supplied.

6. The signal processing circuit according to claim 4 , wherein

the charge/discharge circuit has a capacitor serving as the electricity storage element having a first end electrically connected to the reference potential,

a first resistor having a first end electrically connected to a first power source potential,

a first switch having an input/output path electrically connected between a second end of the first resistor and a second end of the capacitor and having a control terminal to which the first time-length signal is supplied,

a second resistor having a first end electrically connected to a second power source potential, and

a second switch having an input/output path electrically connected between the second end of the capacitor and a second end of the second resistor and having a control terminal to which the control signal is supplied.

7. The signal processing circuit according to claim 1 , wherein

the second circuit has a second logic circuit configured to subject the plurality of second time-length signals output respectively from the plurality of first circuits to a logic operation.

8. The signal processing circuit according to claim 7 , wherein the second logic circuit is a logical addition circuit.

9. The signal processing circuit according to claim 7 , wherein the second circuit further includes:

a first sequential circuit configured to retain and output a potential determined in advance at a rising edge of an output signal of the second logic circuit, and

a second sequential circuit configured to retain and output the potential determined in advance at a decaying edge of the output signal of the second logic circuit.

10. The signal processing circuit according to claim 9 , wherein each of the first sequential circuit and the second sequential circuit is a flip-flop.

11. The signal processing circuit according to claim 4 , wherein the reference potential is supplied from a single constant voltage source to the plurality of first circuits.

12. The signal processing circuit according to claim 4 , wherein

the comparison circuit is further configured to:

acquire offset information based on null output of the second time-length signal; and

output the second time-length signal based on the offset information.

13. A signal processing device, comprising:

a plurality of multiply-accumulation operation circuits each configured to:

subject each of a plurality of signals to a first multiply-accumulation operation to subject each of the plurality of signals to multiplication by a first-group coefficient and then accumulation to output each of a plurality of first signals; and

subject each of the plurality of signals to a second multiply-accumulation operation to subject each of the plurality of signals to multiplication by a second-group coefficient and then accumulation to output each of a plurality of second signals; and

a signal processing circuit having a plurality of first circuits and a second circuit, wherein

the plurality of first circuits is electrically connected to the plurality of multiply-accumulation operation circuits, respectively,

each of the plurality of first circuits includes:

a first-time-length-signal output circuit configured to output a first time-length signal representing a time length between first timing at which a first signal of the plurality of first signals changes and second timing at which a second signal of the plurality of second signals changes; and

a second-time-length-signal output circuit configured to output the first time-length signal as a second time-length signal at timing based on a control signal,

the second circuit is configured to output the second time-length signal having the longest time length among a plurality of second time-length signals output from the plurality of first circuits, respectively.

14. The signal processing device according to claim 13 , further comprising

a second signal processing circuit electrically connected between a multiply-accumulation operation circuit of the plurality of multiply-accumulation operation circuits and the signal processing circuit, wherein the second signal processing circuit is configured to:

subject the first signal and the second signal to a non-linear function operation; and

output the first signal and the second signal to the signal processing circuit.

15. A signal processing method, comprising:

outputting, by a first time-length signal output circuit of a plurality of first circuits, a first time-length signal representing a time length between first timing at which a first input signal changes and second timing at which a second input signal changes;

outputting, by a second time-length signal output circuit of the plurality of first circuits, the first time-length signal as a second time-length signal at timing based on a control signal; and

outputting, by a second circuit, the second time-length signal having the longest time length among a plurality of second time-length signals output respectively from the plurality of first circuits.