IP Library › Granted Patent US 12,158,542
Granted Patent B2
US 12,158,542 · App. 17/250,343 · Granted Dec 3, 2024

Light-receiving element and distance-measuring module

Inventors: Ryota Watanabe (Kanagawa, JP); Toshifumi Wakano (Kanagawa, JP); Takuro Murase (Kanagawa, JP); Takuya Maruyama (Kanagawa, JP); Tsutomu Imoto (Kanagawa, JP); Yuji Isogai (Kanagawa, JP)
Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
G01S7/4811G01S7/4863H01L31/02005H01L23/585
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Quick Facts
Patent No.
US 12,158,542
App. No.
17/250,343
Granted
Dec 3, 2024
Kind
B2
Abstract

The present technology relates to a light-receiving element and a distance-measuring module for enabling improvement of characteristics. A light-receiving element includes an on-chip lens, a wiring layer, and a semiconductor layer arranged between the on-chip lens and the wiring layer, the semiconductor layer includes a first voltage application portion to which a first voltage is applied, a second voltage application portion to which a second voltage different from the first voltage is applied, a first charge detection portion arranged around the first voltage application portion, and a second charge detection portion arranged around the second voltage application portion, and the wiring layer includes at least one ground line having a wider line width than a power supply line. The present technology can be applied to, for example, a light-receiving element that generates distance information by a ToF method.

Claims (63)

1. A light-receiving element, comprising:

an on-chip lens;

a wiring layer; and

a semiconductor layer between the on-chip lens and the wiring layer, wherein

the semiconductor layer includes:

a first voltage application portion to which a first voltage is applied;

a second voltage application portion to which a second voltage different from the first voltage is applied;

a first charge detection portion arranged around the first voltage application portion; and

a second charge detection portion around the second voltage application portion, and

the wiring layer includes two ground lines in one pixel column in a specific layer, wherein

the two ground lines are symmetrically arranged, and

at least one ground line of the two ground lines has a wider line width than a power supply line.

2. The light-receiving element according to claim 1 , wherein

the wiring layer further includes at least one layer that has a reflective member, and

the reflective member overlaps with the first charge detection portion and the second charge detection portion in a plan view.

3. The light-receiving element according to claim 1 , wherein

the wiring layer further includes at least one layer that has a light-shielding member, and

the light-shielding member overlaps with the first charge detection portion and the second charge detection portion in a plan view.

4. The light-receiving element according to claim 1 , further comprising

a vertical signal line configured to transmit a signal detected in the first charge detection portion or the second charge detection portion, wherein

both sides of the vertical signal line are ground lines having a same line width.

5. The light-receiving element according to claim 4 , wherein

one pixel column has four vertical signal lines, and

signals of two rows are simultaneously transmitted.

6. The light-receiving element according to claim 1 , wherein

the at least one ground line has a plurality of gaps inside.

7. The light-receiving element according to claim 6 , wherein

the plurality of gaps is regularly arrayed in a vertical direction.

8. The light-receiving element according to claim 1 , further comprising wherein

a switching transistor, a transfer transistor, a reset transistor, an amplification transistor, and a selection transistor in a vertical direction in order from a side close to an intermediate line with reference to the intermediate line of the first voltage application portion and the second voltage application portion.

9. The light-receiving element according to claim 1 , wherein

at least one of the power supply line or the at least one ground line includes a horizontal wire that extends in a horizontal direction in a first wiring layer and a vertical wire that extends in a vertical direction in a second wiring layer, and

the horizontal wire and the vertical wire are wired to form a grid in a plan view in a pixel array unit.

10. The light-receiving element according to claim 1 , wherein

the first voltage application portion and the second voltage application portion are respectively configured by a first P-type semiconductor region and a second P-type semiconductor region in the semiconductor layer.

11. The light-receiving element according to claim 1 , wherein

the first voltage application portion and the second voltage application portion are respectively configured by a first transfer transistor and a second transfer transistor in the semiconductor layer.

12. A distance-measuring module, comprising:

a light-receiving element including:

an on-chip lens;

a wiring layer; and

a semiconductor layer between the on-chip lens and the wiring layer, wherein

the semiconductor layer includes:

a first voltage application portion to which a first voltage is applied;

a second voltage application portion to which a second voltage different from the first voltage is applied;

a first charge detection portion around the first voltage application portion; and

a second charge detection portion around the second voltage application portion, and

the wiring layer includes two ground lines in one pixel column in a specific layer, wherein

the two ground lines are symmetrically arranged, and

at least one ground line of the two ground lines has a wider line width than a power supply line;

a light source configured to radiate irradiation light in which brightness periodically varies; and

a light-emission control unit configured to control irradiation timing of the irradiation light.

13. A light-receiving element, comprising:

an on-chip lens;

a wiring layer; and

a semiconductor layer between the on-chip lens and the wiring layer, wherein

the semiconductor layer includes:

a first voltage application portion to which a first voltage is applied;

a second voltage application portion to which a second voltage different from the first voltage is applied;

a first charge detection portion around the first voltage application portion; and

a second charge detection portion around the second voltage application portion,

the wiring layer includes at least one ground line that has a wider line width than a power supply line, and

both sides of a vertical signal line are ground lines having a same line width, wherein the vertical signal line is configured to transmit a signal detected in the first charge detection portion or the second charge detection portion.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 7, 2021
From: WATANABE, RYOTA; WAKANO, TOSHIFUMI; MURASE, TAKURO; MARUYAMA, TAKUYA; IMOTO, TSUTOMU; ISOGAI, YUJI
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 054846/0691 →
Priority Claims (1)
JP 2018-135398 · Jul 18, 2018 · national
Continuity (1)
Related Publication 20210270941A1 · Sep 2, 2021