IP Library › Granted Patent US 11,965,970
Granted Patent B2
US 11,965,970 · App. 17/250,672 · Granted Apr 23, 2024

Light receiving element and ranging system

Inventor: Tatsuki Nishino (Kanagawa, JP)
Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
G01S17/931G01J1/44G01S7/4863H01L31/107G01J2001/442G01J2001/4466G01J2001/4473
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Quick Facts
Patent No.
US 11,965,970
App. No.
17/250,672
Granted
Apr 23, 2024
Kind
B2
Abstract

A light receiving element and a ranging system is provided which achieve improvement of pixel characteristics while allowing variation in a breakdown voltage of an SPAD. The light receiving element includes a pixel array in which a plurality of pixels is arranged in a matrix, and a pixel driving unit configured to control respective pixels of the pixel array to be active pixels or non-active pixels. The pixel includes an SPAD, a transistor connected to the SPAD in series, an inverter configured to output a detection signal indicating incidence of a photon on the SPAD, a first transistor which is switched on or off in accordance with control of the pixels to be the active pixels or the non-active pixels, and a second transistor connected to the first transistor in series.

Claims (38)

1. A light receiving element, comprising:

a pixel array in which a plurality of pixels is arranged in a matrix; and

a pixel driving unit configured to control respective pixels of the pixel array to be active pixels or non-active pixels,

wherein the pixel includes:

a single photon avalanche diode (SPAD);

a resistance component connected to the SPAD in series;

an output unit configured to output a detection signal indicating incidence of a photon on the SPAD;

a first transistor which is switched on or off in accordance with control of the pixels to be the active pixels or the non-active pixels; and

a second transistor connected to the first transistor in series,

wherein the second transistor is a diode-connected transistor.

2. The light receiving element according to claim 1 ,

wherein the second transistor is connected to a body diode of the first transistor in parallel.

3. The light receiving element according to claim 2 ,

wherein a current flowing direction in the second transistor is opposite to a current flowing direction in the body diode.

4. A light receiving element, comprising:

a pixel array in which a plurality of pixels is arranged in a matrix; and

a pixel driving unit configured to control respective pixels of the pixel array to be active pixels or non-active pixels,

wherein the pixel includes:

a single photon avalanche diode (SPAD);

a resistance component connected to the SPAD in series;

an output unit configured to output a detection signal indicating incidence of a photon on the SPAD;

a first transistor which is switched on or off in accordance with control of the pixels to be the active pixels or the non-active pixels; and

a second transistor connected to the first transistor in series,

wherein the output unit includes a CMOS inverter, and

a threshold voltage of the second transistor is lower than a threshold voltage of the CMOS inverter.

5. A ranging system, comprising:

an illumination apparatus configured to radiate irradiation light; and

a light receiving element configured to receive reflected light of the irradiation light,

wherein the light receiving element includes:

a pixel array in which a plurality of pixels is arranged in a matrix; and

a pixel driving unit configured to control respective pixels of the pixel array to be active pixels or non-active pixels, and

the pixel includes:

a single photon avalanche diode (SPAD);

a resistance component connected to the SPAD in series;

an output unit configured to output a detection signal indicating incidence of a photon on the SPAD;

a first transistor which is switched on or off in accordance with control of the pixels to be the active pixels or the non-active pixels; and

a second transistor connected to the first transistor in series,

wherein the second transistor is a diode-connected transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 18, 2021
From: NISHINO, TATSUKI
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 055319/0801 →
Priority Claims (1)
JP 2018-163586 · Aug 31, 2018 · national
Continuity (1)
Related Publication 20220350027A1 · Nov 3, 2022
Cited By (1)
US 12,607,503