Method for manufacturing a CFET device
A method for manufacturing a CFET device comprises forming a substrate of the double semi-conductor on insulator type, successively comprising, from the base to the surface thereof: a carrier substrate, a first electrically insulating layer, a first single-crystal semiconductor layer, a second electrically insulating layer and a second single-crystal semiconductor layer. Slices are formed into the substrate to the first electrically insulating layer so as to form at least one fin (F). A channel of a first transistor is formed in the first semiconductor layer and a channel of a second transistor is formed opposite the first transistor in the second semiconductor layer. Formation of the substrate of the double semi-conductor on insulator type comprises: a first and a second step of transferring a layer and thermal processing at a temperature that is sufficiently high to smooth the first single-crystal semiconductor layer to a roughness lower than 0.1 nm RMS.
1. A method of fabricating a CFET device, comprising:
forming a double semiconductor-on-insulator substrate comprising, in succession, from its base to its surface: a carrier substrate, a first electrically insulating layer, a first single-crystal semiconductor layer, a second electrically insulating layer and a second single-crystal semiconductor layer;
forming trenches from the surface of the substrate, to the first electrically insulating layer, so as to form at least one fin (F), and
in each fin (F), forming a channel of a first transistor in the first semiconductor layer and a channel of a second transistor of opposite type to the first transistor in the second semiconductor layer,
the formation of the double semiconductor-on-insulator substrate comprising:
a first layer-transfer step to transfer the first electrically insulating layer and the first single-crystal semiconductor layer to the carrier substrate, so as to form a first semiconductor-on-insulator substrate, the first layer-transfer step comprising a heat treatment at a sufficiently high temperature to smooth the first single-crystal semiconductor layer to a roughness lower than 0.1 nm RMS, and
after the heat treatment, a second layer-transfer to transfer the second electrically insulating layer and the second single-crystal semiconductor layer to the first single-crystal semiconductor layer of the first semiconductor-on-insulator substrate.
2. The method of claim 1 , wherein the trenches are formed by etching, the first electrically insulating layer forming a stop layer for the etching.
3. The method of claim 2 , wherein the thickness of the first and second single-crystal semiconductor layers is between 25 and 40 nm.
4. The method of claim 3 , wherein the thickness of the second electrically insulating layer is between 10 and 30 nm.
5. The method of claim 4 , wherein the first and second semiconductor layers comprise silicon doped with opposite polarities.
6. The method of claim 1 , wherein the first and second semiconductor layers comprise silicon having different crystal orientations.
7. The method of claim 1 , wherein the first and second semiconductor layers comprise different materials.
8. The method of claim 1 , wherein the semiconductor layer in which a channel of an n-type transistor is disposed comprises strained silicon.
9. The method of claim 1 , wherein the semiconductor layer in which a channel of a p-type transistor is disposed comprises silicon-germanium.
10. The method of claim 1 , wherein the first and/or second electrically insulating layers comprise silicon oxide (SiO 2 ).
11. The method of claim 1 , wherein the first and second electrically insulating layers comprise different materials.
12. The method of claim 1 , wherein the first electrically insulating layer comprises a high-k material.
13. The method of claim 1 , wherein the second electrically insulating layer comprises a low-k material.
14. The method of claim 1 , further comprising epitaxially growing a semiconductor layer on the carrier substrate.
15. The method of claim 1 , wherein the carrier substrate comprises at least one COP-free CZ silicon layer.
16. The method of claim 1 , wherein the smoothing heat treatment of the first single-crystal semiconductor layer is carried out at a temperature between 1000 and 1200° C., for a time between 10 and 120 minutes.
17. The method of claim 1 , further comprising a heat treatment for finishing the second single-crystal semiconductor layer at a temperature between 1100 and 1250° C., carried out for less than one minute.
18. The method of claim 1 , wherein the thickness of the first and second single-crystal semiconductor layers is between 25 and 40 nm.
19. The method of claim 1 , wherein the thickness of the second electrically insulating layer is between 10 and 30 nm.
20. The method of claim 1 , wherein the first and second semiconductor layers comprise silicon doped with opposite polarities.