Application-transparent near-memory processing architecture with memory channel network

1. A system comprising:

a printed circuit board (PCB) on which is disposed memory components; and

a processor disposed on the PCB and coupled between the memory components and a host memory controller of a host system across one or more global memory channels, the processor comprising:

a memory channel network (MCN) memory controller to handle memory requests associated with the memory components;

a local buffer;

a core coupled to the MCN memory controller and the local buffer, the core to execute an operating system (OS) including a network software layer used for running a distributed computing framework; and

an MCN driver coupled to the core and to the local buffer, the MCN driver to:

receive a network packet from the network software layer;

store the network packet in the local buffer; and

assert a value of a transmit polling field of an entry in the local buffer for the network packet, the asserted value to facilitate detection by a host driver of the host system that the network packet is available for transmission to the host system.

2. The system of claim 1 , wherein the PCB is a dual in-line memory module (DIMM) and the memory components comprise a plurality of double data rate (DDR) random access memory (RAM) components.

3. The system of claim 1 , wherein the MCN driver includes an interrupt handler to:

receive an interrupt from the local buffer indicating a second network packet is stored in a receiving buffer of the local buffer;

transfer, from the receiving buffer, the second network packet to the MCN memory controller for storage in the memory components; and

send, from the receiving buffer, the second network packet to an upper network layer for processing.

4. The system of claim 1 , wherein the processor further comprises a host protocol interface coupled between the host memory controller and the core, the host protocol interface adapted with a protocol engine to repeat command/address (C/A) signals and data input/output (DQ) signals to and from the host memory controller.

5. The system of claim 4 , wherein the host protocol interface is to, in response to receipt of a memory write request from the host memory controller:

retrieve a write command from the memory write request;

retrieve a host physical address (HPA) and data from the C/A and DQ signals, respectively, from the host memory controller;

translate the HPA to a local address of the local buffer; and

write the data to the local buffer.

6. The system of claim 4 , wherein the host protocol interface is to, in response to receipt of a memory read request from the host memory controller:

retrieve a read command from the memory read request;

retrieve a host physical address (HPA) from the C/A signals of the host protocol interface;

translate the HPA to a local address of the local buffer;

read the data from the local buffer; and

generate second DQ signals, onto the host protocol interface, following a host protocol.

7. The system of claim 4 , wherein the local buffer comprises:

a transmission buffer to store MCN messages to be transmitted to the host memory controller;

a receiving buffer to store MCN messages that are received from the host memory controller; and

a set of control fields comprising:

transmit start pointers pointing to a start of transmission data stored in the transmission buffer;

transmit end pointers pointing to an end of the transmission data stored in the transmission buffer;

receive start pointers pointing to a start of received data stored in the receiving buffer; and

receive end pointers pointing to an end of the received data stored in the receiving buffer.

8. The system of claim 1 , wherein the local buffer is further to send a hardware interrupt signal to a host processor coupled to the host memory controller, the hardware interrupt signal to notify the host processor of a received network packet in the local buffer.