Method for manufacturing a memory device and memory device manufactured through the same method

1. A method for manufacturing a 3D vertical array of memory cells, comprising:

forming, on a substrate, a stack of dielectric material layers comprising alternating first and second dielectric material layers;

forming a trench through the stack of dielectric material layers, the trench exposing the substrate;

filling the trench with a third dielectric material;

forming holes through the stack of dielectric material layers, the holes exposing the substrate, wherein forming the holes through the stack of dielectric material layers comprises forming the holes in the third dielectric material filling the trench;

selectively removing the second dielectric material layers through the holes to form cavities between adjacent first dielectric material layers;

filling the cavities with a conductive material through the holes to form corresponding conductive material layers;

forming first memory cell access lines from the conductive material layers;

carrying out a conformal deposition of a chalcogenide material through the holes;

forming memory cell storage elements from the deposited chalcogenide material; and

filling the holes with conductive material to form corresponding second memory cell access lines.

2. The method of claim 1 , wherein selectively removing the second dielectric material layers through the holes comprises providing an etching agent through the holes.

3. The method of claim 1 , wherein selectively removing the second dielectric material layers through the holes comprises performing a selective isotropic etching operation.

4. The method of claim 1 , wherein forming the trench through the stack of dielectric material layers comprises performing a selective vertical etching operation.

5. The method of claim 1 , wherein forming the holes in the third dielectric material filling the trench comprises performing a selective vertical etching operation.

6. The method of claim 1 , wherein the substrate comprises the third dielectric material.

7. The method of claim 1 , wherein forming the trench through the stack of dielectric material layers subdivides each second dielectric material layer in a corresponding first portion of the second dielectric material and a corresponding second portion of the second dielectric material, filling the cavities with a conductive material causing:

the replacement of each corresponding first portion of the second dielectric material layer with a corresponding first portion of conductive material layer, and

the replacement of each corresponding second portion of the second dielectric material layer with a corresponding second portion of conductive material layer.

8. The method of claim 7 , wherein forming the first memory cell access lines from the conductive material layers comprises forming the first memory cell access lines from the corresponding first portion of the conductive material layer and the corresponding second portion of the conductive material layer.

9. The method of claim 1 , further comprising:

forming a further trench through the stack of dielectric material layers in an access portion of the 3D vertical array of memory cells;

filling the further trench with the third dielectric material;

forming further holes in the third dielectric material filling the further trench;

selectively removing the second dielectric material layers in the access portion through the further holes to form further cavities between adjacent first dielectric material layers in the access portion; and

filling the further cavities with a conductive material through the further holes to form corresponding conductive material layers in the access portion.

10. The method of claim 1 , further comprising forming a plurality of conductive contacts extending through the substrate, each conductive contact being associated to a respective second access memory line.

11. The method of claim 10 , wherein forming the holes through the stack of dielectric material layers comprises forming holes at the conductive contacts to expose the conductive contacts.

12. The method of claim 11 , wherein filling the holes with conductive material comprises contacting the conductive contacts with the conductive material.

13. A method for manufacturing a 3D vertical array of memory cells, comprising:

forming, on a substrate, a stack of dielectric material layers comprising alternating first and second dielectric material layers;

forming a trench through the stack of dielectric material layers, the trench exposing the substrate, and

filling the trench with a third dielectric material

forming holes through the stack of dielectric material layers, the holes exposing the substrate, wherein forming the holes through the stack of dielectric material layers comprises forming the holes in the third dielectric material filling the trench;

selectively removing the second dielectric material layers through the holes to form cavities between adjacent first dielectric material layers;

filling the cavities with a conductive material through the holes to form corresponding conductive material layers for forming a first access line to memory cells;

forming memory cell storage elements though recesses at the holes; and

filling the holes with conductive material to form corresponding second memory cell access lines.

14. The method of claim 13 , further comprising forming a data storage element of a memory cell by recessing the conductive material layers at the holes and carrying out a conformal deposition of a chalcogenide material through the recesses at the holes in order to fill the recesses with the chalcogenide material.

15. The method of claim 14 , wherein forming the plurality of recesses comprises performing an isotropic etching operation in sidewalls of the holes.

16. The method of claim 13 , wherein the first dielectric material layer comprises silicon dioxide and the second dielectric material layer comprises silicon nitride.