Configurable in memory computing engine, platform, bit cells and layouts therefore

1. An in-memory computing architecture, comprising:

a compute-in-memory (CIM) array of bit-cells configured to receive parallel bit-wise input signals via a first CIM array dimension and to drive one or more accumulation signals via a second CIM array dimension, wherein each plurality of bit-cells associated with a common analog accumulation signal forms a respective CIM channel configured to provide analog representation of a respective portion of a multi bit computation output signal; and

control circuitry configured to cause the CIM array to perform a multi-bit computing operation on the input and accumulation signals using single-bit internal circuits and signals;

wherein each bit-cell in said CIM array of bit-cells has a bit-cell circuit configuration comprising:

a bit-cell storage circuit coupled to at least one bit-cell compute device; and

a bit-cell capacitor coupled to the bit-cell compute device, the bit-cell capacitor being further coupled to one or more additional capacitors corresponding to other bit-cell capacitors without a switch between the bit-cell capacitors.

2. The in-memory computing architecture of claim 1 , further comprising a reshaping buffer, configured to reshape a sequence of received data words to form the parallel bit-wise input signals.

3. The in-memory computing architecture of claim 1 , further comprising analog-to-digital converter (ADC) circuitry configured to process the plurality of CIM channel output signals to provide thereby a sequence of multi-bit output words.

4. The in-memory computing architecture of claim 3 , further comprising a near-memory computing path configured to provide said sequence of multi-bit output words as a computing result.

5. The in-memory computing architecture of claim 3 , wherein said ADC circuitry comprises, for each CIM channel, a respective ADC configured to digitize the CIM channel output signal, and a respective shift register configured to impart a respective binary weighting to the digitized CIM channel output signal to form thereby a respective portion of a multi-bit output word.

6. The in-memory computing architecture of claim 3 , wherein said ADC circuitry comprises, for each of a plurality of subsets of said CIM channels, a respective ADC configured to digitize a weighted analog summation of the CIM channel output signals of the respective subset of CIM channels to form thereby a respective portion of a multi-bit output word.

7. The in-memory computing architecture of claim 1 , further comprising a sparsity controller configured to mask zero-valued elements of the parallel bit-wise input signals such that said multi-bit computing operation avoids processing zero-valued elements of the parallel bit-wise input signals.

8. The in-memory computing architecture of claim 1 , wherein the input signals and accumulation signals are combined with existing signals within the memory.

9. The in-memory computing architecture of claim 1 , wherein the input signals and accumulation signals are separate from existing signals within the memory.

10. The in-memory computing architecture of claim 3 , wherein each ADC and respective accumulation signal forms an in-memory computing channel.

11. The in-memory computing architecture of claim 4 , wherein said near-memory computing path comprises one or more of digital barrel shifters, multiplexers, accumulators, look-up tables, and non-linear function elements.

12. The in-memory computing architecture of claim 10 , wherein the multi-bit computing operation of the CIM array comprises bit-parallel/bit-serial (BPBS) computing,

wherein said bit-parallel computing comprises:

loading different matrix-element bits into respective in-memory computing channels;

using respective barrel shifters, barrel shifting digitized outputs from the computing channels to implement thereby corresponding bit weightings; and

using respective accumulators, performing digital accumulation over all of the computing channels to yield a multi-bit matrix-element compute result; and

wherein said bit-serial computing comprises:

individually applying each bit of a vector element to the loaded matrix-element bits and storing each resulting digitized output; and

using respective barrel shifters, barrel shifting the stored digitized outputs associated with each vector element bit prior to a digital accumulation with stored digitized outputs corresponding to subsequent input vector bits.

13. The in-memory computing architecture of claim 4 , where the near-memory computing path is physically aligned with the in-memory-computing architecture to increase throughput therethrough.

14. The in-memory computing architecture of claim 1 , further comprising one or more configurable finite-state machines (FSMs) configured to control computational operation of the in-memory computing architecture.

15. The in-memory computing architecture of claim 14 , where the FSM controlling the computational operation is configured to control parallel computing hardware utilized by some or all of a plurality of in-memory computing channels.

16. The in-memory computing architecture of claim 14 , wherein the FSMs control computations in accordance with software instructions loaded in a local memory.

17. The in-memory computing architecture of claim 2 , wherein the reshaping buffer is configured to convert external digital words of a first precision into a high-dimensionality input vector.

18. The in-memory computing architecture of claim 17 , wherein the reshaping buffer is configured to provide bits of the input vector elements in a sequenced and parallel manner to the CIM array.

19. The in-memory computing architecture of claim 2 , wherein the reshaping buffer is configured for alignment input data to ensure a desired utilization and throughput of in-memory-computing operations.

20. The in-memory computing architecture of claim 2 , wherein the reshaping buffer is configured to enable reuse and shifting of input data in accordance with convolutional-neural-network operations.

21. The in-memory computing architecture of claim 1 , wherein the bit-cell circuit configuration further comprises a cathode plate of the bit-cell capacitor being coupled to the bit-cell compute device.

22. The in-memory computing architecture of claim 1 , wherein the bit-cell circuit configuration further comprises an anode plate of the bit-cell capacitor being coupled to the additional capacitors.

23. The in-memory computing architecture of claim 1 , wherein the bit-cell circuit configuration further comprises the bit-cell compute device being configured to perform a compute operation with two operands.

24. The in-memory computing architecture of claim 1 , wherein the bit-cell circuit configuration enables implementation of XNOR or AND operations between data stored and data inputted.

25. The in-memory computing architecture of claim 1 , wherein a bit-cell circuit configuration comprising an interleaved layout for at least two bit-cells in which respective bit-cell capacitors are coupled together in at least two separate sets to enable thereby corresponding separate computations.

26. The in-memory computing architecture of claim 25 , wherein the sets of coupled bit-cell capacitors are laid out above one or more bit-cell transistors.

27. The in-memory computing architecture of claim 25 , wherein the bit-cells comprise charge-domain in-memory-computing bit-cells that drive one plate of a respective local capacitor, and where coupling to other bit-cell capacitors is achieved at another plate of the respective local capacitor.

28. The in-memory computing architecture of claim 27 wherein the charge-domain in-memory-computing bit-cells are configured to implement XNOR or AND operations between stored data and inputted data.

29. The in-memory computing architecture of claim 25 , wherein an interleaved layout for charge-domain in-memory-computing bit-cells is provided such that bit-cell capacitors are coupled in multiple different sets configured to be selectively coupled via one or more peripheral switches.

30. The in-memory computing architecture of claim 25 , wherein an interleaved layout for charge-domain in-memory-computing bit-cells is provided such that bit-cell capacitors are coupled in multiple different sets so that there are X sets for X-way interleaving, wherein X in an integer greater than one.

31. The in-memory computing architecture of claim 26 , wherein a layout for charge-domain in-memory-computing bit-cells is provided such that different sets of coupled capacitors are laid out above the bit-cell transistors.