IP Library › Granted Patent US 11,990,778
Granted Patent B2
US 11,990,778 · App. 17/258,957 · Granted May 21, 2024

Secondary battery protection circuit and secondary battery anomaly detection system

Inventors: Takayuki Ikeda (Kanagawa, JP); Munehiro Kozuma (Kanagawa, JP); Takanori Matsuzaki (Kanagawa, JP); Ryota Tajima (Kanagawa, JP); Shunpei Yamazaki (Tokyo, JP); Yuki Okamoto (Kanagawa-ken, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H02J7/0031H01M10/4235H02J7/0036
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Quick Facts
Patent No.
US 11,990,778
App. No.
17/258,957
Granted
May 21, 2024
Kind
B2
Abstract

Safety is secured in such a manner that an anomaly of a secondary battery is detected with a protection circuit, for example, a phenomenon that lowers the safety of a secondary battery, particularly a micro short circuit, is detected early, and users are warned or the use of the secondary battery is stopped. A secondary battery protection circuit includes a first memory circuit electrically connected to a secondary battery, a comparison circuit electrically connected to the first memory circuit, a second memory circuit electrically connected to the comparison circuit, and a power-off switch electrically connected to the second memory circuit. The power-off switch is electrically connected to the secondary battery, and the first memory circuit includes a first transistor including an oxide semiconductor and retains a voltage value of the secondary battery in an analog manner.

Claims (46)

1. A secondary battery protection circuit comprising:

a first memory circuit electrically connected to a secondary battery;

a comparison circuit electrically connected to the first memory circuit;

a second memory circuit electrically connected to the comparison circuit; and

a power-off switch electrically connected to the second memory circuit,

wherein the power-off switch is electrically connected to the secondary battery,

wherein the first memory circuit comprises a first transistor comprising an oxide semiconductor, and

wherein the first transistor is configured to retain a voltage value of the secondary battery in an analog manner.

2. The secondary battery protection circuit according to claim 1 ,

wherein the second memory circuit comprises a second transistor comprising an oxide semiconductor, and

wherein the second transistor is configured to retain data of the power-off switch.

3. The secondary battery protection circuit according to claim 1 ,

wherein the comparison circuit is electrically connected to the secondary battery, and when a voltage drop of the secondary battery occurs, an output signal of the comparison circuit is inverted, an anomaly is detected, and the power-off switch is brought into an off state.

4. The secondary battery protection circuit according to claim 1 ,

wherein the first memory circuit is subjected to writing every period Δt and the comparison circuit compares a voltage value of the secondary battery and a value retained in the first memory circuit.

5. The secondary battery protection circuit accord according to claim 1 ,

wherein the oxide semiconductor comprises any one of indium, gallium, and zinc.

6. A secondary battery anomaly detection system comprising the secondary battery protection circuit according to claim 1 :

wherein the first memory circuit retains an offset voltage value of the secondary battery,

wherein a warning of an anomaly is given to a user at a point in time when the voltage value of the secondary battery becomes largely different from the offset voltage value of the secondary battery.

7. A secondary battery anomaly detection system comprising the secondary battery protection circuit according to claim 1 :

wherein the first memory circuit retains an offset voltage value of the secondary battery,

wherein charging stops at a point in time when the voltage value of the secondary battery becomes largely different from the offset voltage value of the secondary battery.

8. A secondary battery anomaly detection system comprising the secondary battery protection circuit according to claim 1 :

wherein the first memory circuit retains an offset voltage value of the secondary battery,

wherein a charging condition is changed in accordance with the number of times or the strength of an anomaly point where the voltage value of the secondary battery becomes largely different from the offset voltage value of the secondary battery.

9. A secondary battery protection circuit comprising:

a first comparison circuit electrically connected to a first memory circuit;

a second memory circuit electrically connected to a secondary battery;

a second comparison circuit electrically connected to the second memory circuit; and

an OR circuit to which an output of the first comparison circuit and an output of the second comparison circuit are each input,

wherein the first memory circuit comprises a first transistor comprising an oxide semiconductor,

wherein the first transistor is configured to retain a voltage value of the secondary battery in an analog manner,

wherein the second memory circuit comprises a second transistor comprising an oxide semiconductor, and

wherein the second transistor is configured to retain a voltage value of the secondary battery in an analog manner with a timing different from that of the first memory circuit.

10. The secondary battery protection circuit according to claim 9 ,

wherein the oxide semiconductor includes any one of indium, gallium, and zinc.

11. A secondary battery anomaly detection system comprising the secondary battery protection circuit according to claim 9 :

wherein one of the first memory circuit and the second memory circuit retains an offset voltage value of the secondary battery,

wherein a warning of an anomaly is given to a user at a point in time when the voltage value of the secondary battery becomes largely different from the offset voltage value of the secondary battery.

12. A secondary battery anomaly detection system comprising the secondary battery protection circuit according to claim 9 :

wherein one of the first memory circuit and the second memory circuit retains an offset voltage value of the secondary battery,

wherein charging stops at a point in time when the voltage value of the secondary battery becomes largely different from the offset voltage value of the secondary battery.

13. A secondary battery anomaly detection system comprising the secondary battery protection circuit according to claim 9 :

wherein one of the first memory circuit and the second memory circuit retains an offset voltage value of the secondary battery,

wherein a charging condition is changed in accordance with the number of times or the strength of an anomaly point where the voltage value of the secondary battery becomes largely different from the offset voltage value of the secondary battery.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 3, 2021
From: IKEDA, TAKAYUKI; KOZUMA, MUNEHIRO; MATSUZAKI, TAKANORI; TAJIMA, RYOTA; YAMAZAKI, SHUNPEI; OKAMOTO, YUKI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 055477/0361 →
Priority Claims (2)
JP 2018-131018 · Jul 10, 2018 · national
JP 2018-141302 · Jul 27, 2018 · national
Continuity (1)
Related Publication 20210126473A1 · Apr 29, 2021