Method for testing a power module

1. A method for testing a power module, the power module is located in a testing motherboard, the method comprising:

connecting both ends of an output capacitor of the power module to a load meter, respectively;

inputting an input signal of the power module to a first channel of an oscillometer, inputting an enable signal of the power module to a second channel of the oscillometer, inputting a PowerGood signal of the power module to a third channel of the oscillometer, and inputting an output signal of the power module to a fourth channel of the oscillometer;

setting testing items of the first, second and third channels of the oscillometer as Max, and setting testing items of the fourth channel of the oscillometer as Max/Min/Pk-Pk/Rise/Fall;

controlling the load meter to be powered on and setting the load meter to a static load mode;

adjusting the load meter to a no-load state, adjusting the oscillometer to be triggered by rising edges of the enable signal, controlling the testing motherboard to be powered on, capturing and storing power-on waveforms of the input signal, the enable signal, the PowerGood signal and the output signal of the power module at the no-load state, adjusting the oscillometer to be triggered by falling edges of the enable signal, controlling the testing motherboard to be powered off, and capturing and storing power-off waveforms of the input signal, the enable signal, the PowerGood signal and the output signal of the power module at the no-load state;

determining, by a tester, whether a power-on sequence and a power-off sequence of the power module are normal and determining whether an overshoot voltage value and an undershoot voltage value of the power module are normal based on the power-on waveforms and the power-off waveforms of the four channels signals of the power module stored by the load meter under the no-load state;

adjusting the load meter to a full-load state, adjusting the oscillometer to be triggered by the rising edges of the enable signal, controlling the testing motherboard to be powered on, capturing and storing power-on waveforms of the input signal, the enable signal, the PowerGood signal and the output signal of the power module at the full-load state, adjusting the oscillometer to be triggered by the falling edges of the enable signal, controlling the testing motherboard to be powered off, and capturing and storing power-off waveforms of the input signal, the enable signal, the PowerGood signal and the output signal of the power module at the full-load state; and

determining, by a tester, whether the power-on sequence and power-off sequence of the power module are normal and determining whether the overshoot voltage value and undershoot voltage value of the power module are normal based on the power-on waveforms and the power-off waveforms of the four channels of signals of the power module stored by the load meter under the full-load state.

2. The method claim 1 , further comprising:

adjusting the load meter to a half-load state, adjusting the oscillometer to be triggered by the rising edges of the enable signal, controlling the testing motherboard to be powered on, capturing and storing power-on waveforms of the input signal, the enable signal, the PowerGood signal and the output signal of the power module at the half-load state, adjusting the oscillometer to be triggered by the falling edges of the enable signal, controlling the testing motherboard to be powered off, and capturing and storing power-off waveforms of the input signal, the enable signal, the PowerGood signal and the output signal of the power module at the half-load state; and

determining, by a tester, whether a power-on sequence and a power-off sequence of the power module are normal and determining whether the overshoot voltage value and undershoot voltage value of the power module are normal based on the power-on waveforms and the power-off waveforms of the four channels of signals of the power module stored by the load meter under the half-load state.

3. The method of claim 2 , further comprising:

determining whether a rising time and a falling time of the output signal of the power module meet preset requirements based on the power-on waveforms and the power-off waveforms of the output signal of the power module stored by the load meter under the no-load state;

and/or, determining whether a rising time and a falling time of the output signal of the power module meet preset requirements based on the power-on waveforms and the power-off waveforms of the output signal of the power module stored by the load meter under the full-load state;

and/or, determining whether a rising time and a falling time of the output signal of the power module meet preset requirements based on the power-on waveforms and the power-off waveforms of the output signal of the power module stored by the load meter under the half-load state.

4. The method of claim 2 , further comprising:

comparing a rising time and a falling time of the output signal of the power module with a preset rising time threshold to determine whether the rising time of the output signal of the power module meets the preset requirements under the half-load state; and

comparing a falling time of the output signal of the power module with a preset falling time threshold to determine whether the falling time of the output signal of the power module meets the preset requirements at the half-load state.

5. The method of claim 1 , wherein inputting an input signal of the power module to a first channel of an oscillometer, inputting an enable signal of the power module to a second channel of the oscillometer, inputting a PowerGood signal of the power module to a third channel of the oscillometer, and inputting an output signal of the power module to a fourth channel of the oscillometer further includes:

connecting an input end of the power module to the first channel of the oscillometer through a first single-ended probe;

connecting an enable signal end of the power module to the second channel of the oscillometer through a second single-ended probe;

connecting a PowerGood signal end of the power module to the third channel of the oscillometer through a third single-ended probe; and

connecting an output end of the power module to the fourth channel of the oscillometer through a fourth single-ended probe.

6. The method of claim 1 , wherein inputting an input signal of the power module to a first channel of an oscillometer, inputting an enable signal of the power module to a second channel of the oscillometer, inputting a PowerGood signal of the power module to a third channel of the oscillometer, and inputting an output signal of the power module to a fourth channel of the oscillometer further includes:

connecting an input end of the power module to the first channel of the oscillometer through a first single-ended probe;

connecting an enable signal end of the power module to the second channel of the oscillometer through a second single-ended probe;

connecting an PowerGood signal end of the power module to the third channel of the oscillometer through a third single-ended probe; and

connecting one end of the output capacitor of the power module to a positive input end of a differential probe, connecting the other end of the output capacitor of the power module to a negative input end of the differential probe, and connecting an output end of the differential probe to the fourth channel of the oscillometer.

7. The method of claim 1 , further comprising:

comparing a rising time of the output signal of the power module with a preset rising time threshold to determine whether the rising time of the output signal of the power module meets preset requirements under the no-load state;

comparing a falling time of the output signal of the power module with a preset falling time threshold to determine whether the falling time of the output signal of the power module meets preset requirements at the no-load state;

a rising time of the output signal of the power module with a preset rising time threshold to determine whether the rising time of the output signal of the power module meets preset requirements under the full-load state; and

comparing a falling time of the output signal of the power module with a preset falling time threshold to determine whether the falling time of the output signal of the power module meets the preset requirements at the full-load state.

8. A method for testing a power module located in a testing motherboard, the method comprising:

connecting both ends of an output capacitor of the power module to a load meter, respectively;

inputting an input signal of the power module to a first channel of an oscillometer, inputting an enable signal of the power module to a second channel of the oscillometer, inputting a PowerGood signal of the power module to a third channel of the oscillometer, and inputting an output signal of the power module to a fourth channel of the oscillometer;

setting testing items of the first, second and third channels of the oscillometer as Max, and setting testing items of the fourth channel of the oscillometer as Max/Min/Pk-Pk/Rise/Fall;

controlling the load meter to be powered on and setting the load meter to a static load mode;

adjusting the load meter to a no-load state, adjusting the oscillometer to be triggered by rising edges of the enable signal, controlling the testing motherboard to be powered on, capturing and storing power-on waveforms of the input signal, the enable signal, the PowerGood signal and the output signal of the power module at the no-load state, adjusting the oscillometer to be triggered by falling edges of the enable signal, controlling the testing motherboard to be powered off, and capturing and storing power-off waveforms of the input signal, the enable signal, the PowerGood signal and the output signal of the power module at the no-load state; and

determining, by a tester, whether a power-on sequence and a power-off sequence of the power module are normal and determining whether an overshoot voltage value and an undershoot voltage value of the power module are normal based on the power-on waveforms and the power-off waveforms of the four channels of signals of the power module stored by the load meter under the no-load state.

9. The method of claim 8 , further comprising:

adjusting the load meter to a full-load state, adjusting the oscillometer to be triggered by the rising edges of the enable signal, controlling the testing motherboard to be powered on, capturing and storing power-on waveforms of the input signal, the enable signal, the PowerGood signal and the output signal of the power module at the full-load state, adjusting the oscillometer to be triggered by the falling edges of the enable signal, controlling the testing motherboard to be powered off, and capturing and storing power-off waveforms of the input signal, the enable signal, the PowerGood signal and the output signal of the power module at the full-load state; and

determining, by a tester, whether the power-on sequence and power-off sequence of the power module are normal and determining whether the overshoot voltage value and undershoot voltage value of the power module are normal based on the power-on waveforms and the power-off waveforms of the four channels of signals of the power module stored by the load meter under the full-load state.

10. The method of claim 9 , further comprising:

determining whether a rising time and a falling time of the output signal of the power module meet preset requirements based on the power-on waveforms and the power-off waveforms of the output signal of the power module stored by the load meter under the full-load state.

11. The method for testing of claim 9 , further comprising:

comparing a rising time of the output signal of the power module with a preset rising time threshold to determine whether the rising time of the output signal of the power module meets preset requirements under the no-load state;

comparing a falling time of the output signal of the power module with a preset falling time threshold to determine whether the falling time of the output signal of the power module meets preset requirements at the no-load state;

comparing a rising time of the output signal of the power module with a preset rising time threshold to determine whether the rising time of the output signal of the power module meets preset requirements under the full-load state; and

comparing a falling time of the output signal of the power module with a preset falling time threshold to determine whether the falling time of the output signal of the power module meets preset requirements at the full-load state.

12. The method of claim 9 , further comprising:

adjusting the load meter to a half-load state, adjusting the oscillometer to be triggered by the rising edges of the enable signal, controlling the testing motherboard to be powered on, capturing and storing power-on waveforms of the input signal, the enable signal, the PowerGood signal and the output signal of the power module at the half-load state, adjusting the oscillometer to be triggered by the falling edges of the enable signal, controlling the testing motherboard to be powered off, and capturing and storing power-off waveforms of the input signal, the enable signal, the PowerGood signal and the output signal of the power module at the half-load state.

13. The method of claim 12 , further comprising:

determining whether a rising time of the output signal of the power module meet preset requirements based on the power-on waveforms and the power-off waveforms of the output signal of the power module stored by the load meter under the half-load state;

determining whether a power-on sequence and a power-off sequence of the power module are normal and determining whether the overshoot voltage value and undershoot voltage value of the power module are normal based on the power-on waveforms and the power-off waveforms of the four channels of signals of the power module stored by the load meter under the half-load state.

14. The method of claim 8 , further comprising:

determining whether a rising time and a falling time of the output signal of the power module meet preset requirements based on the power-on waveforms and the power-off waveforms of the output signal of the power module stored by the load meter under the no-load state.

15. A method for testing a power module located in a testing motherboard, the method comprising:

connecting both ends of an output capacitor of the power module to a load meter, respectively;

inputting an input signal of the power module to a first channel of an oscillometer, inputting an enable signal of the power module to a second channel of the oscillometer, inputting a PowerGood signal of the power module to a third channel of the oscillometer, and inputting an output signal of the power module to a fourth channel of the oscillometer;

adjusting the load meter to a no-load state, capturing and storing power-on waveforms of the input signal, the enable signal, the PowerGood signal and the output signal of the power module at the no-load state;

adjusting the load meter to a full-load state, capturing and storing power-on waveforms of the input signal, the enable signal, the PowerGood signal and the output signal of the power module at the full-load state; and

determining, by a tester, whether a power-on sequence and a power-off sequence of the power module are normal and determining whether an overshoot voltage value and an undershoot voltage value of the power module are normal based on the power-on waveforms and power-off waveforms of the four channels of signals of the power module stored by the load meter under the no-load state and the full-load state.