Communication device, and electronic device comprising same
A communication device is disclosed. The disclosed communication device comprises: a transmission circuit for generating a transmission signal by using a first field effect transistor (FET) and a signal inputted from a first control circuit, and transmitting the transmission signal to a second control circuit; and a reception circuit for generating a reception signal by using a second field effect transistor (FET) and a signal received from the second control circuit, and outputting the reception signal to the first control circuit.
1. An electronic device, comprising:
a sub processor configured to control an operation on a pre-set function of the electronic device;
a main processor configured to control the sub processor; and
a communication device configured to transfer a control signal of the main processor to the sub processor, and receive a response signal of the sub processor,
wherein the communication device comprises:
a transmission circuit configured to generate a transmission signal by using a control signal input from the main processor and a first field effect transistor (FET), and transmit the transmission signal to the sub processor; and
a reception circuit configured to generate a reception signal by using a signal received from the sub processor and a second FET, and output the reception signal to the main processor,
wherein the transmission circuit further comprises:
a first resistance configured for one end to be connected to the main processor, and another end to be connected to a pre-set first voltage;
a second resistance configured for one end to be connected to a drain of the first FET, and another end to be connected to a pre-set second voltage;
a first low pass filter (LPF) circuit configured for one end to be connected to the drain of the first FET, and another end to be connected to the sub processor; and
the first FET is configured for a gate to be connected to the pre-set first voltage, and a source to be connected to the main processor,
wherein components of the reception circuit are arranged from the main processor to have a symmetrical structure with components of the transmission circuit arranged from the main processor.
2. The electronic device of claim 1 , wherein the transmission circuit is configured to generate, based on a voltage level of the main processor being lower than a voltage level of the sub processor, the transmission signal by performing a level shift to the signal inputted from the main processor, and
wherein the reception circuit is configured to generate, based on the voltage level of the main processor being lower than the voltage level of the sub processor, the reception signal by performing a level shift to the signal received from the sub processor.
3. The electronic device of claim 1 , wherein the pre-set first voltage has a voltage magnitude corresponding to a high level of a signal input from the main processor.
4. The electronic device of claim 1 , wherein the pre-set second voltage has a voltage magnitude corresponding to a high level of a signal input from the sub processor.
5. The electronic device of claim 1 , wherein the pre-set second voltage has a voltage magnitude which is the same as the pre-set first voltage.
6. The electronic device of claim 1 , wherein the first FET is a N-Channel Metal Oxide Semiconductor (NMOS) transistor.
7. The electronic device of claim 1 , wherein the first LPF circuit comprises:
a third resistance configured for one end to be connected to the drain of the first FET, and another end to be connected to the sub processor; and
a first capacitor configured for one end to be connected to the drain of the first FET, and another end to be grounded, and
the first LPF circuit is configured to filter a high frequency corresponding to a communication speed of the electronic device.
8. The electronic device of claim 1 , wherein the reception circuit further comprises:
a fourth resistance configured for one end to be connected to the main processor, and another end to be connected to a pre-set third voltage;
a fifth resistance configured for one end to be connected to a drain of the second FET, and another end to be connected to a pre-set fourth voltage; and
a second LPF circuit configured for one end to be connected to the drain of the second FET, and another end to be connected to the sub processor, and
the second FET is configured for a gate to be connected to the pre-set third voltage, and a source to be connected to the main processor.
9. The electronic device of claim 8 , wherein the pre-set third voltage has a voltage magnitude corresponding to a high level of a signal input from the main processor.
10. The electronic device of claim 8 , wherein the pre-set fourth voltage has a voltage magnitude which is the same as the pre-set third voltage.
11. The electronic device of claim 8 , wherein:
the second LPF circuit comprises:
a sixth resistance configured for one end to be connected to the drain of the second FET, and another end to be connected to the sub processor; and
a second capacitor configured for one end to be connected to the drain of the second FET, and another end to be grounded, and
the second LPF circuit is configured to filter a high frequency corresponding to a communication speed of the electronic device.