IP Library Granted Patent US 11,476,153
Granted Patent B2
US 11,476,153 · App. 17/276,107 · Granted Oct 18, 2022

Method for producing an advanced substrate for hybrid integration

Inventor: Walter Schwarzenbach (Saint Nazaire les Eymes, FR)
Assignee: Soitec
H01L21/76254H01L21/84H01L27/1207H01L21/02532
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Quick Facts
Patent No.
US 11,476,153
App. No.
17/276,107
Granted
Oct 18, 2022
Kind
B2
Abstract

A method of forming a substrate comprises providing a receiver substrate and a donor substrate successively comprising: a carrier substrate, a sacrificial layer, which can be selectively etched in relation to an active layer, and a silicon oxide layer, which is arranged on the active layer. A cavity is formed in the oxide layer to form a first portion that has a first thickness and a second portion that has a second thickness greater than the first thickness. The cavity is filled with a polycrystalline silicon filling layer to form a second free surface that is continuous and substantially planar. The receiver substrate and the donor substrate are assembled at the second free surface, and the carrier substrate is eliminated while preserving the active layer and the sacrificial layer.

Claims (23)

1. A method of producing a substrate, comprising the following steps:

a) providing a receiver substrate and a donor substrate comprising:

a carrier substrate;

an active layer made from a single-crystal semiconductor material; and

a sacrificial layer made from a material that can be selectively etched with respect to the active layer, the sacrificial layer being interposed between the carrier substrate and the active layer;

a silicon oxide layer with a free surface and arranged so that the active layer is interposed between the sacrificial layer and the oxide layer;

b) forming a cavity in the oxide layer, the cavity having an opening that lies flush with the free surface so that the oxide layer comprises a first portion having a first thickness and placed between the cavity and the active layer, and a second portion having a second thickness greater than the first thickness, the second portion being placed between the free surface and the active layer;

c) forming a polycrystalline silicon filling layer so as to completely fill the cavity and form a continuous and substantially planar second free surface, the second free surface comprising at least one first polycrystalline silicon surface;

d) assembling the receiver substrate and the donor substrate on the second free surface; and

e) removing the carrier substrate after step d) while preserving the active layer and the sacrificial layer.

2. The method of claim 1 , further comprising, after step e), a step of selectively etching the sacrificial layer while at the same time preserving the active layer.

3. The method of claim 2 , wherein the assembling step d) comprises a step of bonding by molecular adhesion.

4. The method of claim 1 , further comprising the following steps:

b0) forming, before step b) and after step a), a weakened zone in the carrier substrate, the weakened zone being substantially planar and located in the vicinity of the interface between the sacrificial layer and the carrier substrate; and

e0) fracturing the carrier substrate along the weakened zone after step d).

5. The method of claim 4 , wherein the carrier substrate comprises a material that can be selectively etched with respect to the material of the sacrificial layer, the method further comprising selectively etching the rest of the carrier substrate placed on the sacrificial layer, after the fracturing step e0).

6. The method of claim 4 , wherein the filling layer is formed by chemical vapor deposition at a temperature between 150° C. and 250° C.

7. The method of claim 1 , wherein the single-crystal silicon active layer is produced by epitaxy.

8. The method of claim 1 , wherein the filling layer covers the silicon oxide layer.

9. The method of claim 8 , wherein a polycrystalline silicon layer is formed on the second portion of the silicon oxide layer, the polycrystalline silicon layer having a thickness of between 1 nm and 1000 nm, and wherein the second free surface formed following step c) consists essentially of polycrystalline silicon.

10. The method of claim 1 , wherein step c) comprises thinning of filling layer and/or the oxide layer so that the second free surface also comprises a second silicon oxide surface.

11. The method of claim 1 , wherein the active layer preserved after step e) is locally thinned to locally reduce the thickness of the active layer.

12. The method of claim 1 , wherein the assembling step d) comprises a step of bonding by molecular adhesion.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 15, 2021
From: SCWARZENBACH, WALTER
To: SOITEC
Reel/Frame 055586/0694 →
Priority Claims (1)
FR 1800972 · Sep 14, 2018 · national
Continuity (1)
Related Publication 20220051934A1 · Feb 17, 2022