METHOD FOR CREATION OF DIFFERENT DESIGNS BY COMBINING A SET OF PRE-DEFINED DISJOINT MASKS
Described are methods for enabling the creation of multiple similar designs by utilizing sets of multiple, disjoint fabrication masks. A first set of device features may be formed from a material layer in a first portion of a die area of a semiconductor substrate based on a first photolithographic exposure. A second set of device features may be formed from the material layer in a second portion of the die area of the semiconductor substrate based on a second photolithographic exposure after the first photolithographic exposure. The first portion of the die area and the second portion of the die area may be non-overlapping.
1 - 20 . (canceled)
21 . A method comprising:
forming a first set of device features from a material layer in a first portion of a die area of a semiconductor substrate based on a first photolithographic exposure; and
forming a second set of device features from the material layer in a second portion of the die area of the semiconductor substrate based on a second photolithographic exposure after the first photolithographic exposure;
wherein the first portion of the die area and the second portion of the die area are non-overlapping.
22 . The method of claim 20 ,
wherein forming the first set of device features comprises applying a first photolithographic mask, and
wherein forming the second set of device features comprises applying a second photolithographic mask.
23 . The method of claim 20 ,
wherein forming at least one of the first set of device features and the second set of device features comprises applying a positive photoresist.
24 . The method of claim 20 ,
wherein the material layer comprises a metal layer.
25 . The method of claim 20 ,
wherein the material layer comprises a redistribution layer.
26 . The method of claim 20 ,
wherein a portion of the semiconductor substrate under at least one of the first set of device features and the second set of device features comprises an analog signaling region.
27 . The method of claim 20 , wherein the semiconductor substrate comprises a silicon wafer.
28 . The method of claim 20 , wherein the die area comprises features for a programmable semiconductor interposer.
29 . The method of claim 20 , comprising:
mounting a first chiplet in the first portion of the die area; and
mounting a second chiplet in the second portion of the die area.
30 . A method comprising:
applying a first photolithographic pattern to a first portion of a single-die area of a semiconductor wafer using a first photolithographic mask;
applying a second photolithographic pattern to a second portion of the single-die area of the semiconductor wafer using a second photolithographic mask, the second portion of the single-die area being spaced from the first portion of the single-die area; and
processing the semiconductor wafer to form at least one of a first set of device features in the first portion of the single-die area, and a second set of device features in the second portion of the single-die area.
31 . The method of claim 30 ,
wherein at least a portion of the first set of device features and at least a portion of the second set of device features are formed in at least one of: a metal layer, and a redistribution layer.
32 . The method of claim 0 ,
wherein at least one of the first photolithographic pattern and the second photolithographic pattern is applied to a positive photoresist.
33 . The method of claim 0 ,
wherein a portion of the semiconductor wafer under at least one of the first set of device features and the second set of device features comprises an analog signaling region.
34 . The method of claim 0 ,
wherein the single-die area comprises features for a programmable semiconductor interposer.
35 . The method of claim 0 , comprising:
mounting a first chiplet in the first portion of the die area; and
mounting a second chiplet in the second portion of the die area.
36 . A method comprising:
placing a first photolithographic mask into a first alignment with respect to a first portion of a single-die area of a semiconductor wafer;
performing a first photolithographic exposure of the semiconductor wafer through the first photolithographic mask;
placing a second photolithographic mask into a second alignment with respect to a second portion of the single-die area of the semiconductor wafer; and
performing a second photolithographic exposure of the semiconductor wafer through the second photolithographic mask,
wherein the first portion of the single-die area and the second portion of the single-die area are disjoint.
37 . The method of claim 0 , comprising:
processing the semiconductor wafer to form at least one of a first set of device features in the first portion of the single-die area, and a second set of device features in the second portion of the single-die area.
38 . The method of claim 0 ,
wherein a portion of the semiconductor wafer under at least one of the first set of device features and the second set of device features comprises an analog signaling region.
39 . The method of claim 0 ,
wherein the single-die area comprises features for a programmable semiconductor interposer.
40 . The method of claim 0 , comprising:
mounting a first chiplet in the first portion of the die area; and
mounting a second chiplet in the second portion of the die area.