Pixel driving circuit, array substrate and display device
View Patent ↗A pixel driving circuit, an array substrate and a display device are provided. The pixel driving circuit includes a first interlayer dielectric layer and a second interlayer dielectric layer. The first interlayer dielectric layer is arranged on the side of a gate layer lead away from a base substrate and is formed with a first via hole exposing the gate layer lead. The second interlayer dielectric layer is arranged on the side of the first interlayer dielectric layer away from the base substrate and is formed with a second via hole exposing the first via hole. A source drain layer lead is arranged on the side of the second interlayer dielectric layer away from the base substrate and is electrically connected to the gate layer lead through the first via hole and the second via hole.
1. A pixel driving circuit, comprising:
a base substrate;
a gate layer lead, arranged on a side of the base substrate;
a first interlayer dielectric layer, arranged on a side of the gate layer lead away from the base substrate, and formed with a first via hole exposing a contact area of the gate layer lead;
a second interlayer dielectric layer, arranged on a side of the first interlayer dielectric layer away from the base substrate, and formed with a second via hole exposing the first via hole; and
a source drain layer lead, arranged on a side of the second interlayer dielectric layer away from the base substrate, and electrically connected to the gate layer lead through the first via hole and the second via hole;
wherein the first interlayer dielectric layer and the second interlayer dielectric layer are formed with the same material by different processes in order to have different densities, so that the first via hole and the second via hole are formed to have different slope angles.
2. The pixel driving circuit according to claim 1 , wherein a slope angle of the first via hole is less than a slope angle of the second via hole.
3. The pixel driving circuit according to claim 2 , wherein the slope angle of the first via hole is between 20° and 45°.
4. The pixel driving circuit according to claim 2 , wherein the slope angle of the second via hole is between 45° and 90°.
5. The pixel driving circuit according to claim 2 , wherein an edge of the first via hole away from the base substrate overlaps with an edge of the second via hole close to the base substrate.
6. The pixel driving circuit according to claim 1 , wherein an orthographic projection of an edge of the second via hole close to the base substrate on the first interlayer dielectric layer encloses an edge of the first via hole away from the base substrate.
7. The pixel driving circuit according to claim 6 , wherein a slope angle of the first via hole is equal to a slope angle of the second via hole.
8. The pixel driving circuit according to claim 6 , wherein a slope angle of at least one of the first via hole and the second via hole is between 45° and 90°.
9. The pixel driving circuit according to claim 1 , wherein a material of the first interlayer dielectric layer and the second interlayer dielectric layer comprises silicon nitride, silicon oxide or silicon oxynitride.
10. The pixel driving circuit according to claim 1 , wherein the pixel driving circuit further comprises: a transistor, arranged on a side of the base substrate; and
the gate layer lead is electrically connected to the transistor.
11. The pixel driving circuit according to claim 1 , wherein the pixel driving circuit further comprises a driver transistor arranged on a side of the base substrate, and a gate of the driver transistor is electrically connected to the gate layer lead.
12. The pixel driving circuit according to claim 11 , wherein the pixel driving circuit further comprises a storage capacitor, the storage capacitor comprises a first electrode plate, and the first electrode plate is electrically connected to the source drain layer lead.
13. The pixel driving circuit according to claim 12 , wherein the first electrode plate and an active layer of the driver transistor are arranged in the same layer and have the same material.
14. The pixel driving circuit according to claim 12 , wherein the storage capacitor further comprises a second electrode plate, and the second electrode plate and a gate layer of the driver transistor are arranged in the same layer and have the same material.
15. The pixel driving circuit according to claim 1 , wherein the pixel driving circuit further comprises a compensating transistor arranged on a side of the base substrate, and a source of the compensating transistor is electrically connected to the gate layer lead.
16. The pixel driving circuit according to claim 15 , wherein the pixel driving circuit further comprises a storage capacitor, the storage capacitor comprises a second electrode plate, and the second electrode plate is electrically connected to a drain of the compensating transistor.
17. An array substrate, comprising a plurality of pixels, wherein each of the pixels comprises the pixel driving circuit according to claim 1 and a light emitting element connected to the pixel driving circuit.
18. The array substrate according to claim 17 , wherein the plurality of pixels share the same base substrate.
19. The array substrate according to claim 17 , wherein the light emitting element is an organic light emitting diode.
20. A display device, comprising the array substrate according to claim 17 and a driver circuit for driving pixels in the array substrate.