Network-on-chip data processing method and device
The present application relates to a network-on-chip data processing method. The method is applied to a network-on-chip processing system, the network-on-chip processing system is used for executing machine learning calculation, and the network-on-chip processing system comprises a storage device and a calculation device. The method comprises: accessing the storage device in the network-on-chip processing system by means of a first calculation device in the network-on-chip processing system, and obtaining first operation data; performing an operation on the first operation data by means of the first calculation device to obtain a first operation result; and sending the first operation result to a second calculation device in the network-on-chip processing system. According to the method, operation overhead can be reduced and data read/write efficiency can be improved.
1. A network-on-chip (NoC) processing system, comprising a storage device and a plurality of computation devices, wherein the storage device and the plurality of computation devices are arranged on a same chip, at least one computation device is connected to the storage device, and at least two computation devices are directly connected to each other; wherein
the computation device is configured to perform a machine learning computation, and the computation device includes an operation unit and a controller unit, wherein the operation unit includes a primary processing circuit and a plurality of secondary processing circuits,
the controller unit is configured to obtain input data and a computation instruction,
the controller unit is further configured to parse the computation instruction to obtain a plurality of operation instructions, and send the plurality of operation instructions and the input data to the primary processing circuit,
the primary processing circuit is configured to perform preorder processing on the input data, and send the data and the operation instructions among the primary processing circuit and the plurality of secondary processing circuits,
the plurality of secondary processing circuits are configured to perform intermediate computations in parallel according to the data and the operation instructions sent by the primary processing circuit to obtain a plurality of intermediate results, and send the plurality of intermediate results to the primary processing circuit, and
the primary processing circuit is further configured to perform postorder processing on the plurality of intermediate results to obtain a computation result of the computation instruction.
2. The system of claim 1 , wherein any two of the plurality of computation devices are directly connected to each other.
3. The system of claim 1 , wherein the plurality of computation devices include a first computation device and a plurality of second computation devices, wherein the first computation device is connected to the storage device, and at least one of the plurality of second computation devices is connected to the first computation device.
4. The system of claim 3 , wherein at least two of the plurality of second computation devices are connected to each other, and are connected to the storage device through the first computation device.
5. The system of claim 3 , wherein any two of the plurality of second computation devices are directly connected to the first computation device.
6. The system of claim 1 , wherein each of the plurality of computation devices is connected to the storage device, and at least two computation devices are connected to each other.
7. The computation device of claim 1 , wherein the controller unit includes an instruction storage unit, an instruction storage processing unit, and a storage queue unit, wherein
the instruction storage unit is configured to store a computation instruction associated with the artificial neural network operation,
the instruction processing unit is configured to parse the computation instruction to obtain a plurality of operation instructions, and
the storage queue unit is configured to store an instruction queue, wherein the instruction queue includes: a plurality of operation instructions or a computation instruction to be executed in an order of the instruction queue.
8. A neural network chip, comprising a storage device, a plurality of computation devices, a first interconnection device, and a second interconnection device, wherein at least one computation device is connected to the storage device through the first interconnection device, and the plurality of computation devices are connected to each other through the second interconnection device wherein,
the computation device is configured to perform a machine learning computation, and the computation device includes an operation unit and a controller unit, wherein the operation unit includes a primary processing circuit and a plurality of secondary processing circuits,
the controller unit is configured to obtain input data and a computation instruction,
the controller unit is further configured to parse the computation instruction to obtain a plurality of operation instructions, and send the plurality of operation instructions and the input data to the primary processing circuit,
the primary processing circuit is configured to perform preorder processing on the input data, and send the data and the operation instructions among the primary processing circuit and the plurality of secondary processing circuits,
the plurality of secondary processing circuits are configured to perform intermediate computations in parallel according to the data and the operation instructions sent by the primary processing circuit to obtain a plurality of intermediate results, and send the plurality of intermediate results to the primary processing circuit, and
the primary processing circuit is further configured to perform postorder processing on the plurality of intermediate results to obtain a computation result of the computation instruction.
9. An NoC data processing method, wherein the method is used to perform a machine learning operation, and includes:
performing, by a computation device, a machine learning computation, wherein the computation device includes an operation unit and a controller unit, wherein the operation unit includes a primary processing circuit and a plurality of secondary processing circuits;
obtaining, by the controller unit, input data and computation instruction;
parsing, by the controller unit, the computation instruction, obtaining a plurality of operation instructions, and sending the plurality of operation instructions and the input data to the primary processing circuit;
performing, by the primary processing circuit, preorder processing on the input data, and sending the data and the operation instructions among the primary processing circuit and the plurality of secondary processing circuits;
performing, by the plurality of secondary processing circuits, intermediate computations in parallel according to the data and the operation instructions sent by the primary processing circuit, obtaining a plurality of intermediate results, and sending the plurality of intermediate results to the primary processing circuit;
performing, by the primary processing circuit, postorder processing on the plurality of intermediate results and obtaining a computation result of the computation instruction;
accessing a storage device by using a first computation device to obtain first operation data;
performing an operation on the first operation data by using the first computation device to obtain a first operation result; and
sending the first operation result to a second computation device.
10. The method of claim 9 , comprising accessing the storage device by using the second computation device to obtain second operation data.
11. The method of claim 10 , comprising performing an operation on the second operation data and the first operation result by using the second computation device to obtain a second operation result.