Imaging apparatus and electronic device
A first and second pixel units that perform FD addition are provided. The first pixel unit includes: a first switch transistor of which one source/drain electrode is connected to an FD; and a reset transistor that is connected between another source/drain electrode of the first switch transistor and a power supply node. The second pixel unit includes: a second switch transistor of which one source/drain electrode is connected to an FD; a third switch transistor of which one source/drain electrode is connected to another source/drain electrode of the second switch transistor; and a capacitive element that is connected between another source/drain electrode of the third switch transistor and a reference potential node. The respective other source/drain electrodes of the first switch transistor and the second switch transistor are electrically connected with each other.
1. An imaging apparatus comprising a first pixel unit and a second pixel unit, each of which includes a floating diffusion that converts charges, transferred from a light-receiving unit, into voltage, and is configured to selectively perform pixel addition that adds pixel signals by electrically connecting the floating diffusions between pixels, wherein
the first pixel unit includes: a first switch transistor of which one source/drain electrode is connected to a floating diffusion; and a reset transistor that is connected between another source/drain electrode of the first switch transistor and a power supply node,
the second pixel unit includes: a second switch transistor of which one source/drain electrode is connected to a floating diffusion; a third switch transistor of which one source/drain electrode is connected to another source/drain electrode of the second switch transistor; and a capacitive element that is connected between another source/drain electrode of the third switch transistor and a reference potential node, and
the respective other source/drain electrodes of the first switch transistor and the second switch transistor are electrically connected with each other.
2. The imaging apparatus according to claim 1 , wherein
in a case where the pixel addition is not performed, the first pixel unit or the second pixel unit implements high conversion efficiency for the conversion efficiency of the floating diffusion when the first switch transistor or the second switch transistor is in a non-conduction state.
3. The imaging apparatus according to claim 1 , wherein
in a case where the pixel addition is not performed, the first pixel unit and the second pixel unit implement intermediate conversion efficiency for the conversion efficiency of the floating diffusion when the first switch transistor and the second switch transistor are both in a non-conduction state.
4. The imaging apparatus according to claim 1 , wherein
in a case where the pixel addition is not performed, the first pixel unit and the second pixel unit implement low conversion efficiency for the conversion efficiency of the floating diffusion when the first switch transistor, the second switch transistor and the third switch transistor are all in a conduction state.
5. The imaging apparatus according to claim 1 , wherein
the first pixel unit and the second pixel unit perform the pixel addition and implement intermediate conversion efficiency for the conversion efficiency of the floating diffusion when the first switch transistor and the second switch transistor are both in a conduction state.
6. The imaging apparatus according to claim 1 , wherein
the first pixel unit and the second pixel unit perform the pixel addition and implement low conversion efficiency for the conversion efficiency of the floating diffusion when the first switch transistor, the second switch transistor and the third switch transistor are all in a conduction state.
7. The imaging apparatus according to claim 1 , wherein
the capacitive element is disposed so as to be divided into respective pixels of the first pixel unit and the second pixel unit.
8. The imaging apparatus according to claim 7 , wherein
the capacitive element is implemented by coupling capacitance between metal lines.
9. The imaging apparatus according to claim 1 , wherein
each of the first pixel unit and the second pixel unit is constituted of a plurality of pixels, and a floating diffusion is shared by the plurality of pixels.
10. The imaging apparatus according to claim 9 , wherein
the first pixel unit and the second pixel unit perform the pixel addition among pixels having a same color.
11. The imaging apparatus according to claim 1 , wherein
composing elements of the first pixel unit and composing elements of the second pixel unit have a pixel layout ensuring symmetry with respect to the center line between the first pixel unit and the second pixel unit.
12. The imaging apparatus according to claim 11 , wherein
each floating diffusion of the first pixel unit and the second pixel unit is disposed at a position that is closer to the center line between the first pixel unit and the second pixel unit than each center of the first pixel unit and the second pixel unit respectively.
13. The imaging apparatus according to claim 1 , wherein
each of the first pixel unit and the second pixel unit has a back-illuminated pixel structure.
14. An electronic device equipped with an imaging apparatus, the imaging apparatus comprising a first pixel unit and a second pixel unit, each of which includes a floating diffusion that converts charges, transferred from a light-receiving unit, into voltage, and is configured to selectively perform pixel addition that adds pixel signals by electrically connecting the floating diffusions between pixels, wherein
the first pixel unit includes: a first switch transistor of which one source/drain electrode is connected to a floating diffusion; and a reset transistor that is connected between another source/drain electrode of the first switch transistor and a power supply node,
the second pixel unit includes: a second switch transistor of which one source/drain electrode is connected to a floating diffusion; a third switch transistor of which one source/drain electrode is connected to another source/drain electrode of the second switch transistor; and a capacitive element that is connected between another source/drain electrode of the third switch transistor and a reference potential node, and
the respective other source/drain electrodes of the first switch transistor and the second switch transistor are electrically connected with each other.