Offset correction circuit

1. An offset correction circuit comprising:

a first correction voltage generation circuit to provide a first correction voltage for correcting an input voltage, the first correction voltage being positive or negative; and

a second correction voltage generation circuit to provide, in accordance with the first correction voltage, a second correction voltage identical in polarity to the first correction voltage, the second correction voltage having a second temperature coefficient reverse in polarity to a first temperature coefficient of the first correction voltage.

2. The offset correction circuit according to claim 1 , wherein

the first correction voltage and the second correction voltage are set to be comparable to each other, and

an absolute value of the second temperature coefficient and an absolute value of the first temperature coefficient are set to be comparable to each other.

3. The offset correction circuit according to claim 1 , further comprising a temperature detection circuit, wherein

the first correction voltage generation circuit controls the first temperature coefficient and the first correction voltage in accordance with a first control signal,

the second correction voltage generation circuit controls the second temperature coefficient and the second correction voltage in accordance with a second control signal, and

at least one of the first control signal and the second control signal is varied in accordance with an output from the temperature detection circuit.

4. The offset correction circuit according to claim 1 , wherein

the first correction voltage generation circuit includes

a first field effect transistor including a gate to receive input of the input voltage,

a second field effect transistor including a gate connected to a node where a first voltage resulting from addition of the first correction voltage to the input voltage is provided,

a first current source group for passage of a comparable current through the first field effect transistor and the second field effect transistor, and

a transistor size ratio control mechanism to variably control a ratio of a transistor size of the second field effect transistor to a transistor size of the first field effect transistor.

5. The offset correction circuit according to claim 4 , wherein

the first and second field effect transistors operate in a subthreshold region.

6. The offset correction circuit according to claim 4 , wherein

in correction of a negative offset voltage, the first correction voltage and the first temperature coefficient are set to be positive by setting of the ratio to be higher than 1 by the transistor size ratio control mechanism, and

in correction of a positive offset voltage, the first correction voltage and the first temperature coefficient are set to be negative by setting of the ratio to be lower than 1 by the transistor size ratio control mechanism.

7. The offset correction circuit according to claim 1 , wherein

the second correction voltage generation circuit includes

a third field effect transistor including a gate to receive input of a voltage resulting from addition of the input voltage and the first correction voltage,

a first variable resistor connected in series to the third field effect transistor between a first node and a second node,

a second variable resistor reverse in polarity of a temperature coefficient to the first variable resistor,

a fourth field effect transistor connected in series to the second variable resistor between a third node and the first node,

a second current source group for passage of a comparable current to each of the second node and the third node, and

an electrical resistance difference variable mechanism to variably control electrical resistance values of the first and second variable resistors such that a voltage difference between the gate of the third field effect transistor and the first node is comparable to a voltage difference between a gate of the fourth field effect transistor and the first node.

8. The offset correction circuit according to claim 7 , wherein

when the first temperature coefficient is positive, the electrical resistance difference variable mechanism controls the electrical resistance values of the first and second variable resistors such that the electrical resistance value of a variable resistor having a negative temperature coefficient, of the first and second variable resistors, is larger than the electrical resistance value of a variable resistor having a positive temperature coefficient, and

when the first temperature coefficient is negative, the electrical resistance difference variable mechanism controls the electrical resistance values of the first and second variable resistors such that the electrical resistance value of the variable resistor having the positive temperature coefficient, of the first and second variable resistors, is larger than the electrical resistance value of the variable resistor having the negative temperature coefficient.

9. The offset correction circuit according to claim 1 , wherein

the second correction voltage generation circuit includes

a third field effect transistor including a gate to receive input of a voltage resulting from addition of the input voltage and the first correction voltage,

a first variable resistor connected in series to the third field effect transistor between a first node and a second node,

a second variable resistor,

a fourth field effect transistor connected in series to the second variable resistor between a third node and the first node,

a second current source group for passage of a comparable current to each of the second node and the third node, and

an electrical resistance difference variable mechanism to variably control electrical resistance values of the first and second variable resistors such that a voltage difference between the gate of the third field effect transistor and the first node is comparable to a voltage difference between a gate of the fourth field effect transistor and the first node, and

the second current source group includes

a first current source to supply an output current in accordance with an electrical resistance value of a bias resistive element to the first node,

a second current source connected to the second node, and

a third current source connected to the third node and being comparable in output current characteristic to the second current source, and

the first current source includes a bias resistance variable mechanism to variably control a polarity of a temperature coefficient of the bias resistive element.

10. The offset correction circuit according to claim 9 , wherein

the bias resistance variable mechanism connects, when the first temperature coefficient is positive, a resistive element having a negative temperature coefficient as the bias resistive element to a path for the output current, and connects, when the first temperature coefficient is negative, a resistive element having a positive temperature coefficient as the bias resistive element to the path for the output current.

11. The offset correction circuit according to claim 7 , wherein

the first variable resistor includes

a plurality of first resistive elements connected in series and parallel between the first node and the second node, and

a plurality of first bypass switches connected in parallel to the first resistive elements, respectively,

the second variable resistor includes

a plurality of second resistive elements connected in series and parallel between the first node and the third node, and

a plurality of second bypass switches connected in parallel to the second resistive elements, respectively, and

a plurality of first bypass switch control signals to control opening and closing of the plurality of first bypass switches and a plurality of second bypass switch control signals to control opening and closing of the plurality of second bypass switches are provided to the second correction voltage generation circuit.