IP Library › Granted Patent US 11,830,792
Granted Patent B2
US 11,830,792 · App. 17/290,087 · Granted Nov 28, 2023

Lead between a plurality of encapsulated MOSFETs

Inventor: Kentaro Nasu (Kyoto, JP)
Assignee: ROHM CO., LTD.
H01L23/49527H01L23/3121H01L23/49513H01L23/49562H01L23/49575H01L24/24H01L24/25H01L24/33H01L24/73H01L24/82H01L24/92H01L25/074H01L23/3135H01L24/29H01L24/30H01L24/32H01L2224/244H01L2224/24175H01L2224/25171H01L2224/29139H01L2224/30505H01L2224/32245H01L2224/3315H01L2224/73267H01L2224/82101H01L2224/82106H01L2224/92244H01L2924/13091H01L2924/15153H01L2924/15162
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Quick Facts
Patent No.
US 11,830,792
App. No.
17/290,087
Granted
Nov 28, 2023
Kind
B2
Abstract

The semiconductor device includes first and second semiconductor elements. Each element has an obverse surface and a reverse surface, with a first electrode arranged on the reverse surface, and with a second electrode arranged on the obverse surface. The semiconductor device further includes: a first lead having an obverse surface and a reverse surface; an insulating layer covering the first lead, the first semiconductor element and the second semiconductor element; a first electrode connected to the second electrode of the first semiconductor element; and a second electrode connected to the first lead. The first semiconductor element and the first lead are bonded to each other with the reverse surface of the first semiconductor element facing the lead obverse surface. The second semiconductor element and the first lead are bonded to each other with the reverse surface of the second semiconductor element facing the lead reverse surface.

Claims (49)

1. A semiconductor device comprising:

a first semiconductor element and a second semiconductor element, each of which has an element obverse surface and an element reverse surface that face opposite to each other in a thickness direction, with an element first electrode arranged on the element reverse surface, and with an element second electrode arranged on the element obverse surface;

a first lead having a lead obverse surface and a lead reverse surface that face opposite to each other in the thickness direction;

an insulating layer covering the first lead, the first semiconductor element, and the second semiconductor element;

a first electrode electrically connected to the element second electrode of the first semiconductor element; and

a second electrode electrically connected to the first lead,

wherein the first semiconductor element and the first lead are bonded to each other with the element reverse surface of the first semiconductor element facing the lead obverse surface,

the second semiconductor element and the first lead are bonded to each other with the element reverse surface of the second semiconductor element facing the lead reverse surface, and

the semiconductor device further comprises a wiring pattern and a via hole,

wherein the insulating layer includes an insulating-layer obverse surface and an insulating-layer reverse surface that face opposite to each other in the thickness direction,

the wiring pattern is formed on at least one of the insulating-layer obverse surface and the insulating-layer reverse surface,

the via hole is open to the insulating-layer obverse surface or the insulating-layer reverse surface, and

the wiring pattern and the via hole forms a conductive path between the element second electrode of the first semiconductor element and the first electrode, and a conductive path between the first lead and the second electrode.

2. The semiconductor device according to claim 1 , wherein the first electrode and the second electrode are arranged on the insulating-layer reverse surface.

3. The semiconductor device according to claim 1 , further comprising

a third electrode electrically connected to the element second electrode of the second semiconductor element,

wherein the element first electrode of the first semiconductor element and the element first electrode of the second semiconductor element are electrically connected to the first lead.

4. The semiconductor device according to claim 1 , further comprising

a second lead electrically connected to the element first electrode of the second semiconductor element, and a fourth electrode electrically connected to the second lead,

wherein the element first electrode of the first semiconductor element is electrically connected to the first lead.

5. The semiconductor device according to claim 4 ,

wherein the first semiconductor element is bonded to the first lead via a conductive bonding layer, and is bonded to the second lead via an insulating bonding layer, and

the second semiconductor element is bonded to the first lead via an insulating bonding layer, and is bonded to the second lead via a conductive bonding layer.

6. The semiconductor device according to claim 4 , wherein the element second electrode of the second semiconductor element is electrically connected to the first electrode.

7. The semiconductor device according to claim 1 , further comprising a third lead electrically connected to the element second electrode of the first semiconductor element and the first electrode, the third lead being covered with the insulating layer.

8. The semiconductor device according to claim 1 , further comprising

a third lead electrically connected to the element first electrode of the second semiconductor element,

wherein the element first electrode of the first semiconductor element is electrically connected to the first lead, and

the third lead is electrically connected to the first electrode.

9. The semiconductor device according to claim 8 ,

wherein the first semiconductor element is bonded to the first lead via a conductive bonding layer, and

the second semiconductor element is bonded to the first lead via an insulating bonding layer, and is bonded to the third lead via a conductive bonding layer.

10. The semiconductor device according to claim 1 , wherein the lead obverse surface includes an obverse-surface recess, and the first semiconductor element is arranged in the obverse-surface recess.

11. The semiconductor device according to claim 1 , wherein the lead reverse surface includes a reverse-surface recess, and the second semiconductor element is arranged in the reverse-surface recess.

12. A semiconductor device comprising:

a first semiconductor element and a second semiconductor element, each of which has an element obverse surface and an element reverse surface that face opposite to each other in a thickness direction, with an element first electrode arranged on the element reverse surface, and with an element second electrode arranged on the element obverse surface;

a first lead having a lead obverse surface and a lead reverse surface that face opposite to each other in the thickness direction;

an insulating layer covering the first lead, the first semiconductor element, and the second semiconductor element;

a first electrode electrically connected to the element second electrode of the first semiconductor element; and

a second electrode electrically connected to the first lead,

wherein the first semiconductor element and the first lead are bonded to each other with the element reverse surface of the first semiconductor element facing the lead obverse surface,

the second semiconductor element and the first lead are bonded to each other with the element reverse surface of the second semiconductor element facing the lead reverse surface, and

the semiconductor device further comprises

a fifth electrode,

wherein each of the first semiconductor element and the second semiconductor element includes an element third electrode arranged on the element obverse surface, and

the fifth electrode is electrically connected to the element third electrode of the first semiconductor element.

13. The semiconductor device according to claim 12 , wherein the element third electrode of the second semiconductor element is electrically connected to the fifth electrode.

14. The semiconductor device according to claim 12 , wherein the first semiconductor element and the second semiconductor element are transistors.

15. The semiconductor device according to claim 12 , further comprising a fourth lead that is electrically connected to the element third electrode of the first semiconductor element and the fifth electrode, and that is covered with the insulating layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2021
From: NASU, KENTARO
To: ROHM CO., LTD.
Reel/Frame 056088/0301 →
Priority Claims (1)
JP 2018-216458 · Nov 19, 2018 · national
Continuity (1)
Related Publication 20210398884A1 · Dec 23, 2021