IP Library › Granted Patent US 12,282,842
Granted Patent B2
US 12,282,842 · App. 17/292,661 · Granted Apr 22, 2025

Neural network processing apparatus, neural network processing method, and neural network processing program

Inventor: Hiroyuki Tokunaga (Tokyo, JP)
Assignee: MAXELL, LTD.
G06N3/063G06F9/5016
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,282,842
App. No.
17/292,661
Granted
Apr 22, 2025
Kind
B2
Abstract

A CNN processing apparatus ( 1 ) includes an input buffer ( 10 ) configured to store an input signal given to a CNN, a storage unit ( 12 ) configured to store a table ( 120 ) in which the input signal given to the CNN and a binary signal corresponding to the value of the input signal are associated with each other, a binary signal acquisition unit ( 13 ) configured to acquire the binary signal corresponding to the value of the input signal stored in the input buffer ( 10 ) by referring to the table ( 120 ), and a convolutional operation unit ( 14 ) configured to perform an operation of the CNN based on the binary signal acquired by the binary signal acquisition unit ( 13 ). The binary signal has an accuracy complying with a predetermined operation accuracy of the CNN.

Claims (22)

1. A neural network processing apparatus comprising:

a first memory configured to store a value given to a neural network;

a second memory configured to store a table in which the value given to the neural network and a binary signal corresponding to the value are associated with each other;

a binary signal acquisition circuit configured to acquire the binary signal corresponding to the value stored in the first memory by referring to the table; and

a neural network operation circuit configured to perform an operation of the neural network based on the binary signal acquired by the binary signal acquisition circuit,

wherein

the binary signal has an accuracy complying with a predetermined operation accuracy of the neural network, and the second memory stores a plurality of tables,

the binary signal acquisition circuit acquires the binary signal corresponding to the value stored in the first memory by referring to one table selected from the plurality of tables;

the neural network processing apparatus further comprising:

a table selector configured to select the one table from the plurality of tables based on a reference concerning the predetermined accuracy in accordance with the value stored in the first memory, wherein the binary signals stored in the plurality of tables have accuracies different from each other,

a determination circuit configured to determine whether the value stored in the first memory is a value representing specific information; and

a converter configured to convert, based on a determination result by the determination circuit, a data type and a size of the value stored in the first memory,

wherein the plurality of tables are provided in correspondence with at least the data types and the sizes of the value given to the neural network,

the table selector selects, from the plurality of tables, a table that matches the data type and the size of the value converted by the converter, and

the binary signal acquisition circuit acquires the binary signal corresponding to the value converted by the converter by referring to the table selected by the table selector.

2. A neural network processing apparatus comprising:

a first memory configured to store a value given to a neural network;

a second memory configured to store a table in which the value given to the neural network and a binary signal corresponding to the value are associated with each other;

a binary signal acquisition circuit configured to acquire the binary signal corresponding to the value stored in the first memory by referring to the table; and

a neural network operation circuit configured to perform an operation of the neural network based on the binary signal acquired by the binary signal acquisition circuit, wherein the binary signal has an accuracy complying with a predetermined operation accuracy of the neural network,

a converter configured to convert a data type and a size of the value stored in the first memory into a data type and a size of an address value in the table stored in the second memory and output the value,

wherein the binary signal acquisition circuit acquires the binary signal corresponding to the value output by the converter.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE CONVEYING PARTY NAME PREVIOUSLY RECORDED AT REEL: 69824 FRAME: 203. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 14, 2025
From: LEAPMIND INC.
To: MAXELL, LTD.
Reel/Frame 070521/0187 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2025
From: LEAPMIND INC.
To: MAXELL, INC.
Reel/Frame 069824/0203 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 11, 2022
From: TOKUNAGA, HIROYUKI
To: LEAPMIND INC.
Reel/Frame 060471/0112 →
Priority Claims (1)
JP 2018-214570 · Nov 15, 2018 · national
Continuity (1)
Related Publication 20220004857A1 · Jan 6, 2022
References Cited (21)
US 10089577B2 · Umuroglu · 2018 [cited by examiner]
US 20160148078A1 · Shen · 2016 [cited by examiner]
US 20200005131A1 · Nakahara et al. · 2020 [cited by applicant]
CN 109844775A · 2019 [cited by applicant]
JP 2006127350A · 2006 [cited by applicant]
JP 2018092377A · 2018 [cited by applicant]
WO 2017073373A1 · 2017 [cited by applicant]
WO 2020100393A1 · 2020 [cited by applicant]
Shin et al (“DNPU: An Energy-Efficient Deep-Learning Processor with Heterogeneous MultiCore Architecture” Oct. 2018) (Year: 2018). [cited by examiner]
Abdelouahab et al (“Accelerating CNN inference on FPGAs: A Survey” Jan. 2018) (Year: 2018). [cited by examiner]
Decision to Grant a Patent of the Japanese Patent Office dated Mar. 22, 2021 for related Japanese Patent Application No. 2020-504042. [cited by applicant]
International Preliminary Report on Patentability of the International Searching Authority dated May 27, 2021 for related PCT Application No. PCT/JP2019/035493. [cited by applicant]
International Search Report and Written Opinion of the International Searching Authority dated Nov. 26, 2019 for related PCT Application No. PCT/JP2019/035493. [cited by applicant]
Notice of Reasons for Refusal of the Japanese Patent Office dated May 10, 2022 for related Japanese Patent Application No. 2021-078513. [cited by applicant]
Notice of Reasons for Refusal of the Japanese Patent Office dated Oct. 27, 2020 for related Japanese Patent Application No. 2020-504042. [cited by applicant]
Rastegari et al., “XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networks”, Computer Vision—ECCV 2016: 14th European Conference Proceedings, Part IV, ECCV, 2016, pp. 525-542. [cited by applicant]
Office Action received for Taiwan Patent Application No. 109103955, mailed on Sep. 5, 2023, 15 pages (7 pages of English Translation and 8 pages of Original Document). [cited by applicant]
Asoh et al., “Deep Learning”, Publisher: Kindai kagaku sha Co., Ltd, Tokyo, Japan, Oct. 31, 2015, p. 156. [cited by applicant]
Shimoda et al., “All Binarized Conventional Neural Network and its Implementation on an FPGA”, IEICE Technical Report, vol. 117, No. 378, Jan. 11, 2018, pp. 7-11 (English Abstract Submitted). [cited by applicant]
Mohammad et al., “XNOR / Net: ImageNet Classification Using Binary Convolutional Neural Networks”, European Conference on Computer Vision, ECCV 2016, pp. 525-542. [cited by applicant]
Notice of Reasons for Refusal of the Japanese Patent Office dated Nov. 15, 2022 for related Japanese Patent Application No. 2021-078513. [cited by applicant]