IP Library › Granted Patent US 12,016,165
Granted Patent B2
US 12,016,165 · App. 17/295,975 · Granted Jun 18, 2024

Shield package

Inventors: Hiroaki Umeda (Kizugawa, JP); Hidetoshi Noguchi (Kizugawa, JP); Hajime Nakazono (Kizugawa, JP); Sougo Ishioka (Kizugawa, JP)
Assignee: Tatsuta Electric Wire & Cable Co., Ltd.
H05K9/003G06K19/06037H01L23/552H05K9/0081H01L2223/54413
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,016,165
App. No.
17/295,975
Granted
Jun 18, 2024
Kind
B2
Abstract

The present invention aims to provide a shield package having a highly distinctive patterned portion formed on a surface of a shield layer. The shield package of the present invention includes a package in which an electronic component is sealed with a sealing material, and a shield layer covering the package, wherein a surface of the shield layer includes a patterned portion and a non-patterned portion other than the patterned portion, and a ratio of Sal (autocorrelation length) of the non-patterned portion to Sal of the patterned portion is as follows: (Sal of non-patterned portion)/(Sal of patterned portion)>4.0.

Claims (27)

1. A shield package comprising:

a package in which an electronic component is sealed with a sealing material; and

a shield layer covering the package,

wherein a surface of the shield layer includes a patterned portion and a non-patterned portion other than the patterned portion, and

a ratio of Sal of the non-patterned portion to Sal of the patterned portion is as follows: (Sal of non-patterned portion)/(Sal of patterned portion)>4.0, where Sal represents an autocorrelation length.

2. The shield package according to claim 1 ,

wherein a surface of the sealing material comprises a drawing area drawn with lines and/or dots by aggregation of multiple grooves, and a non-drawing area other than the drawing area,

multiple depressions originating from the grooves are formed on a surface of the shield layer on the drawing area, and

the depressions are aggregated to draw the patterned portion with lines and/or dots.

3. The shield package according to claim 2 , wherein at least some of the multiple grooves each have a line shape.

4. The shield package according to claim 3 , wherein at least some of the multiple grooves are formed linearly and in parallel to each other.

5. The shield package according to claim 4 , wherein the grooves adjacent to each other are arranged at an interval of 10 to 100 μm.

6. The shield package according to claim 2 , wherein at least some of the multiple grooves are formed in a grid shape.

7. The shield package according to claim 6 , wherein each cell of the grid formed by the grooves has a width of 10 to 100 μm.

8. The shield package according to claim 2 , wherein each groove has a width of 5 to 100 μm.

9. The shield package according to claim 2 , wherein each groove has a depth of 5 μm or more.

10. The shield package according to claim 1 , wherein the patterned portion is a two-dimensional code.

11. A shield package comprising:

a package in which an electronic component is sealed with a sealing material; and

a shield layer covering the package,

wherein a surface of the shield layer includes a patterned portion and a non-patterned portion other than the patterned portion, and

a ratio of Smr1 of the non-patterned portion to Smr1 of the patterned portion is as follows: (Smr1 of non-patterned portion)/(Smr1 of patterned portion)>1.0, where Smr1 represents a ratio of the area of the material at the intersection line which separates the protruding hills from the core surface to the evaluation area.

12. A shield package comprising:

a package in which an electronic component is sealed with a sealing material; and

a shield layer covering the package,

wherein a surface of the shield layer includes a patterned portion and a non-patterned portion other than the patterned portion, and

a ratio of Ssk of the non-patterned portion to Ssk of the patterned portion is as follows: (Ssk of non-patterned portion)/(Ssk of patterned portion)<5.0, where Ssk represents skewness.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 21, 2021
From: UMEDA, HIROAKI; NOGUCHI, HIDETOSHI; NAKAZONO, HAJIME; ISHIOKA, SOUGO
To: TATSUTA ELECTRIC WIRE & CABLE CO., LTD.
Reel/Frame 056312/0261 →
Priority Claims (1)
JP 2018-218409 · Nov 21, 2018 · national
Continuity (1)
Related Publication 20220030751A1 · Jan 27, 2022