Concealed gate terminal semiconductor packages and related methods

1. A semiconductor package comprising:

a lead frame;

one or more semiconductor die coupled with the lead frame; and

an interposer coupled with the lead frame and with at least one of the one or more semiconductor die;

wherein the interposer comprises an electrically conductive material on a first side of the interposer and an electrically insulative material on a second side of the interposer;

wherein the interposer is coupled with the lead frame through the electrically insulative material such that the electrically conductive material is electrically isolated from the lead frame; and

wherein the electrically conductive material forms at least two separated contact pads.

2. The package of claim 1 , wherein the at least two separated contact pads are separated using one of a recess or a raised portion.

3. The package of claim 1 , wherein the interposer is coupled with the lead frame using one of an adhesive, an epoxy, and a solder.

4. The package of claim 1 , wherein the electrically insulative material comprises one of silicon, polyimide, an epoxy, a mold compound, and a ceramic.

5. The package of claim 1 , wherein the electrically conductive material comprises a copper slug.

6. The package of claim 1 , wherein the interposer comprises a flexible tape.

7. The package of claim 1 , wherein the interposer comprises a flexible printed circuit board.

8. The package of claim 1 , wherein the interposer comprises a molded integrated substrate.

9. The package of claim 1 , wherein at least one gate node of a transistor of the one or more semiconductor die is fully enclosed within an encapsulant of the package without the gate node being exposed through the encapsulant.

10. The package of claim 9 , wherein a source pad of the package is exposed through the encapsulant and is electrically coupled with a source node of the transistor.

11. The package of claim 1 , wherein the at least two separated contact pads are separated using an electrically insulative layer coupled over the electrically conductive material.

12. The package of claim 1 , wherein a gate node of one of the one or more semiconductor die is electrically coupled with a driver of the one or more semiconductor die without using a through-silicon via (TSV).

13. A method of forming a semiconductor package comprising:

providing a lead frame;

coupling one or more semiconductor die with the lead frame;

mechanically coupling an interposer with the lead frame and electrically coupling the interposer with at least one of the one or more semiconductor die;

at least partially enclosing the lead frame with an encapsulant, the one or more semiconductor die and the interposer within the encapsulant forming an unsingulated array; and

singulating the array to form a semiconductor package;

wherein the interposer comprises an electrically conductive material on a first side of the interposer and an electrically insulative material on a second side of the interposer;

wherein the interposer is coupled with the lead frame through the electrically insulative material such that the electrically conductive material is electrically isolated from the lead frame; and

wherein the electrically conductive material forms two separated contact pads.

14. The method of claim 13 , wherein the interposer is fully enclosed within the encapsulant without being exposed through the encapsulant after singulation.

15. The method of claim 13 , further comprising fully enclosing at least one gate node of a transistor of the one or more semiconductor die within the encapsulant without the at least one gate node being exposed through the encapsulant after singulation.

16. The method of claim 13 , further comprising exposing a source pad through the encapsulant, the source pad electrically coupled with a source node of a transistor.

17. The method of claim 13 , further comprising electrically coupling a gate node of the one or more semiconductor die with a driver of the one or more semiconductor die without using a through-silicon via (TSV).

18. A semiconductor package comprising:

a lead frame;

at least one transistor coupled with the lead frame;

at least one driver coupled with the lead frame;

an electrical interconnect electrically interconnecting the at least one driver with a gate node of the at least one transistor using an interposer comprising an electrically conductive material; and

an encapsulant at least partially encapsulating the lead frame, the at least one transistor, the at least one driver, and the electrical interconnect;

wherein the gate node is fully encapsulated by the encapsulant; and

wherein the electrically conductive material comprises two separated contact pads.

19. The package of claim 18 , wherein the interposer further comprises an electrically insulative material coupled with the electrically conductive material, wherein the at least one driver is electrically coupled with the gate node through the electrically conductive material, and wherein the electrically insulative material electrically insulates the electrically conductive material from the lead frame.

20. The package of claim 18 , wherein the at least two separated contact pads are separated using one of an electrically insulative layer coupled over the electrically conductive material or a recess formed within the electrically conductive material.